DP83816AVNG National Semiconductor, DP83816AVNG Datasheet - Page 81

• Manufacturer Part Number: DP83816AVNG
• Description: Ethernet Media Access Controller IC
• Manufacturer: National Semiconductor

Specifications of DP83816AVNG

• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Features: Physical Layer
• Package / Case: 144-LQFP
• Package: 144LQFP
• Standard Supported: IEEE 802.3|IEEE 802.3u|IEEE 802.3x
• Communication Mode: Full Duplex|Half Duplex
• Network Interface: MII
• Data Rate: 10|100 Mbps
• Host Interface: PCI
• Operating Supply Voltage: 3.3 V
• Loopback Mode: Internal
• Maximum Power Dissipation: 0.504 W
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

5.0 Buffer Management
5.2 Transmit Architecture
The following figure illustrates the transmit architecture of the DP83816 10/100 Ethernet Controller.
When the CR:TXE bit is set to 1 (regardless of the current state), and the DP83816 transmitter is idle, then DP83816 will
read the contents of the current transmit descriptor into the TxDescCache. The DP83816’s TxDescCache can hold a
single fragment pointer/count combination.
5.2.1 Transmit State Machine
The transmit state machine has the following states:
The transmit state machine manipulates the following internal data spaces:
Inputs to the transmit state machine include the following events:
txIdle
txDescRefr
txDescRead
txFifoBlock
txFragRead
txDescWrite
txAdvance
TXDP
CTDD
TxDescCache
descCnt
fragPtr
txFifoCnt
txFifoAvail
CR:TXE
XferDone
FifoAvail
Transmit Descriptor
The transmit state machine is idle.
Waiting for the "refresh" transfer of the link field of a completed descriptor from the PCI bus.
Waiting for the transfer of a complete descriptor from the PCI bus into the
TxDescriptorCache.
Waiting for free space in the TxDataFIFO to reach TxFillThreshold.
Waiting for the transfer of a fragment (or portion of a fragment) from the PCI bus to the
TxDataFIFO.
Waiting for the completion of the write of the cmdsts field of an intermediate transmit
descriptor (cmdsts.MORE == 1) to host memory.
(transitory state) Examine the link field of the current descriptor and advance to the next
descriptor if link is not NULL.
A 32-bit register that points to the current transmit descriptor.
An internal bit flag that is set when the current transmit descriptor has been completed, and
ownership has been returned to the driver. It is cleared whenever TXDP is loaded with a
new value (either by the state machine, or the driver).
An internal data space equal to the size of the maximum transmit descriptor supported.
Count of bytes remaining in the current descriptor.
Pointer to the next unread byte in the current fragment.
Current amount of data in the txDataFifo in bytes.
Current amount of free space in the txDataFifo in bytes (size of the txDataFifo - txFifoCnt).
Driver asserts the TXE bit in the command register (similar to SONIC).
Completion of a PCI bus transfer request.
TxFifoAvail is greater than TxFillThreshold.
link
cmdsts
ptr
Packet
Software/Memory
(Continued)
Figure 5-4 Transmit Architecture
Hardware
81
Tx DMA
TxHead
link
cmdsts
ptr
Tx Desc Cache
Current Tx Desc Ptr
Tx Data FIFO
www.national.com