DSPIC30F1010-20E/SO Microchip Technology, DSPIC30F1010-20E/SO Datasheet - Page 48

• Manufacturer Part Number: DSPIC30F1010-20E/SO
• Description: 6KB, Flash, 256bytes-RAM, 30MIPS, 21I/O, 16-bit Family,nanoWatt 28 SOIC .300in T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F1010-20E/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 6KB (2K x 24)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

APPENDIX B:
Revision A (February 2007)
This is the initial released version of this document.
Revision B (September 2007)
• Updated paragraph in
• Removed all pin diagrams
• Modified the first sentence in
• Added the following note after the second
• Added the following sentence to the end of the
• Updated instructions in the following tables:
DS70284C-page 48
During Programming”
location of complete pin diagrams
“Overview”
SMPS has Configuration bits stored in seven
16-bit registers. Bold text denotes the change.
paragraph in
Note:
paragraph in
Programming the UNIT ID is similar to program-
ming the Programming Executive (see
Section 12.0 “Programming the Programming
Executive to Memory”
-
-
-
-
-
-
-
-
-
Table 11-4
GOTO instruction in Step 1 and added two
NOPs after BSET and BCLR in Step 12)
Table 11-5
GOTO instruction in Step 1 and added two
NOPs after BSET and BCLR in Step 5 and Step
12)
Table 11-7
GOTO instruction in Step 1, changed BB1B96
to BB1B86 in Step 6, added two NOPs after
BSET and BCLR in Step 8, and changed 9 to
seven in Step 10)
Table 11-8
GOTO instruction in Step 1)
Table 11-9
GOTO instruction in Step 1)
Table 11-10
GOTO instruction in Step 1)
Table 11-11
GOTO instruction in Step 1)
Table 12-1
instruction in Step 1 and added two NOPs after
BSET and BCLR in Step 4 and Step 11)
Table 12-2
GOTO instruction in Step 1)
If user software performs an erase opera-
tion on the configuration fuse, it must be
followed by a write operation to this fuse
with the desired value, even if the desired
value is the same as the state of the
erased fuse.
to read as follows: The dsPIC30F
Section 5.7.1
Section 5.7.5 “User Unit
(removed two NOPs before the
(removed two NOPs before the
(removed two NOPs before the
(removed two NOPs before the
(removed two NOPs before the
(removed two NOPs before the GOTO
(removed two NOPs before the
(removed two NOPs before the
(removed two NOPs before the
REVISION HISTORY
Section 2.2 “Pins Used
to include reference to
for details).
“Overview”:
Section 5.7.1
ID”:
• Replaced the number 9 with the word seven in the
• Changed the max values for parameters T
• Added
Revision C (October 2010)
This version of the document includes the following
updates:
• Updates to text and formatting have been
• Added Note 3 to
• Updated the Device Configuration Register Map
• Updated the assumed FGS register value from
• Updated
• Updated the first paragraph of
• Updated
• Removed the VARIANT bit and updated the bit
• Removed the VARIANT bit and updated the bit
• Added
• Updated Note 3 in
• Removed Note 2 in
• Updated Step 5 and 12 in
• Updated Step 8 in
• Updated Step 8 in
• Updated Step 4 and 11 in
• Added parameters P18b and P19b in
last sentence of the last paragraph of
Section 11.7 “Writing Configuration
and T
incorporated throughout the document
Enhanced ICSP Mode”
(see
0x5 to 0x0 in
Computation”
“Device ID”
definition for the DEVID register in
Device ID Registers
field definition and description for the DEVID
register in
Mode”
Program Memory”
Instruction Execution for Row Erasing Program
Memory
Execution for Writing Configuration registers
Execution for Writing Code Memory
Programming the Programming Executive
AC/DC Characteristics and Timing Requirements
Table
ERA
Appendix A: “Hex File
Figure
Table
Table
in
Table
5-3)
Table 13-1
Section 6.6 “Checksum
11-1:
6-2:
10-1: Device IDs
10-3:
Section 5.2 “Entering
Table
Table
Section 11.3 “Entering ICSP
Checksum Computation
Program Entry After Reset
Section 11.6 “Row Erasing
© 2010 Microchip Technology Inc.
Device ID Bits Description
11-7:
11-8:
Table
Table
Serial Instruction
Serial Instruction
Section 10.0
Format”.
12-1:
11-5:
Table
Serial
Table
Memory”.
10-2:
PROG
13-1: