DSPIC30F2023-20E/PT Microchip Technology, DSPIC30F2023-20E/PT Datasheet - Page 60

• Manufacturer Part Number: DSPIC30F2023-20E/PT
• Description: 12KB, Flash, 512bytes-RAM, 30MIPS, 35I/O, 16-bit Family,nanoWatt 44 TQFP 10x10x1
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2023-20E/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-TQFP, 44-VQFP
• Package: 44TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 35
• Interface Type: I2C/SPI/UART
• On-chip Adc: 12-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

APPENDIX A:
A.1
The checksum computation is described in
“Checksum
16-bit computation can be made for each dsPIC30F
device. Computations for read code protection are
shown both enabled and disabled. The checksum
values assume that the Configuration registers are also
erased. However, when code protection is enabled, the
value of the FGS register is assumed to be 0x5.
TABLE A-1:
DS70102K-page 60
dsPIC30F2010
dsPIC30F2011
dsPIC30F2012
dsPIC30F3010
dsPIC30F3011
dsPIC30F3012
dsPIC30F3013
dsPIC30F3014
dsPIC30F4011
dsPIC30F4012
dsPIC30F4013
dsPIC30F5011
dsPIC30F5013
dsPIC30F5015
Item Description:
SUM(a:b) = Byte sum of locations a to b inclusive (all 3 bytes of code memory)
CFGB
Device
Checksum Computation
Computation”.
= Configuration Block (masked) = Byte sum of ((FOSC&0xC10F) + (FWDT&0x803F) +
(FBORPOR&0x87B3) + (FBS&0x310F) + (FSS&0x330F) + (FGS&0x0007) + (FICD&0xC003))
CHECKSUM COMPUTATION
DEVICE-SPECIFIC
INFORMATION
Disabled
Disabled
Disabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Enabled
Enabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Read Code
Protection
Table A-1
shows how this
CFGB+SUM(0:001FFF)
CFGB
CFGB+SUM(0:001FFF)
CFGB
CFGB+SUM(0:001FFF)
CFGB
CFGB+SUM(0:003FFF)
CFGB
CFGB+SUM(0:003FFF)
CFGB
CFGB+SUM(0:003FFF)
CFGB
CFGB+SUM(0:003FFF)
CFGB
CFGB+SUM(0:003FFF)
CFGB
CFGB+SUM(0:007FFF)
CFGB
CFGB+SUM(0:007FFF)
CFGB
CFGB+SUM(0:007FFF)
CFGB
CFGB+SUM(0:00AFFF)
CFGB
CFGB+SUM(0:00AFFF)
CFGB
CFGB+SUM(0:00AFFF)
CFGB
Section 6.8
Checksum Computation
A.2
A.2.1
The dsPIC30F5011 and dsPIC30F5013 processors
require that the FBS and FSS registers be programmed
with 0x0000 before the device is chip erased. The steps
to perform this action are shown in
A.2.2
The dsPIC30F5011 and dsPIC30F5013 processors
require that the FBS and FSS registers be programmed
with 0x0000 using the PROGC command before the
ERASEB command is used to erase the chip.
dsPIC30F5011 and dsPIC30F5013
ICSP PROGRAMMING
ENHANCED ICSP PROGRAMMING
0xD406
0xD406
0xD406
0xA406
0xA406
0xA406
0xA406
0xA406
0xFC06
0xFC06
0xFC06
Erased
0x0404
0x0404
0x0404
0x0404
0x0404
0x0404
0x0404
0x0404
0x4406
0x0404
0x4406
0x0404
0x4406
0x0404
0x0404
0x0404
0x0404
Value
© 2010 Microchip Technology Inc.
0xAAAAAA at 0x0
Code Address
Table
Value with
and Last
0xD208
0xD208
0xD208
0x0404
0x0404
0x0404
0xA208
0x0404
0xA208
0x0404
0xA208
0x0404
0xA208
0x0404
0xA208
0x0404
0x4208
0x0404
0x4208
0x0404
0x4208
0x0404
0xFA08
0x0404
0xFA08
0x0404
0xFA08
0x0404
11-4.