LMH0030VS National Semiconductor, LMH0030VS Datasheet
LMH0030VS
Specifications of LMH0030VS
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LMH0030VS Summary of contents
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... PLL and the serializer im- prove power supply rejection, output jitter and noise perfor- mance. Order Number LMH0030VS © 2008 National Semiconductor Corporation The LMH0030's internal circuitry is powered from +2.5V and the I/O circuitry from a +3.3V supply. Power dissipation is typically 430mW at 1.485 Gbps including two 75Ω ...
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Typical Application www.national.com 2 20180301 ...
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Block Diagram 3 20180302 www.national.com ...
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... Connection Diagram www.national.com 64-Pin TQFP Order Number LMH0030VS See NS Package Number VEC-64A 4 20180303 ...
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Absolute Maximum Ratings It is anticipated that this device will not be offered in a military qualified version. If Military/Aerospace specified devices are required, please contact the National Semicon- ductor Sales Office / Distributors for availability and specifi- cations. CMOS ...
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Symbol Parameter I (2.5V) Power Supply Current, 2.5V DD Supply, Total I (2.5V) Power Supply Current, 2.5V DD Supply, Total AC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3). Symbol Parameter f Parallel Video ...
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Test Loads Timing Jitter Bandpass 7 20180304 20180306 www.national.com ...
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Test Circuit www.national.com 8 20180307 ...
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Timing Diagram Device Operation The LMH0030 SDTV/HDTV Serializer is used in digital video signal origination equipment: cameras, video tape recorders, telecines and video test and other equipment. It converts par- allel SDTV or HDTV component digital video signals into serial ...
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ACLK when it is being used for control register access. When theANC/CTRL input is a logic-high, ACLK affects only the ancillary data FIFO operation. When the ANC/CTRL input is a logic-low, ACLK affects only the control register opera- tion. ...
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ACLK. Observe the port input hold timing specification. Example: Setup (without enabling) the TPG Mode via the AD port using the 1125 line, 30 frame, 74.25MHz, interlaced com- ...
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MULTI-FUNCTION I/O PORT The Multi-function I/O port can be configured to provide im- mediate access to many control and indicator functions within the LMH0030 configuration and control registers. The indi- vidual pins comprising this port may be assigned as input ...
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This is done so that information like line numbering can be cor- rectly inserted. The PLL itself will have locked in 200 mi- croseconds (HD rates) or less. ...
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It is strongly recommended that V be applied until device initialization and configuration is com- pleted. Example: Enable ...
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TABLE 1. Configuration and Control Data Register Summary Register Function Bits EDH Error (SD) 1 Full-Field Flags 5 Active Picture Flags 5 ANC Flags 5 EDH Force 1 EDH Enable 1 F/F Flag Error 1 A/P Flag Error 1 ANC ...
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Register Function Bits NRZI_Enable 1 LSB_Clipping 1 SYNC_Detect_Enabl 1 e I/O Bus Pin Config. 48 Note 12: Connected to multifunction I/O port at power-on. Note 13 logic-1, OFF = logic-0 (positive logic). Bit 7 Bit 6 EDH 0 ...
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Bit 7 Bit 6 TEST PASS/FAIL TPG ENABLE PATTERN SELECT(5) VIDEO INFO 0 (register address 0Eh) VERT. DITHER VPG FILTER DITHER ENABLE ENABLE ENABLE MULTI-FUNCTION I/O BUS PIN CONFIGURATION I/O PIN 0 CONFIG (register address 0Fh) reserved reserved PIN 0 ...
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TABLE 3. Control Register Addresses Address Register Name Decimal EDH 0 1 EDH 1 2 EDH 2 3 ANC 0 4 ANC 1 5 ANC 2 6 ANC 3 7 ANC 4 8 ANC 5 23 ANC 6 24 SWITCH ...
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DIDs (or DID ranges) into the FIFO. Similarly, the ANC MASK[15: 8-bit word that can be used to selec- tively control loading of packets with specific SDID or DBNs (or SDID or DBN ranges). When ANC MASK[7:0] ...
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Format Code Format Specification [4,3,2,1,0] 01010 SDTV, 36 ITU-R BT 601.5 01011 SDTV, 27 ITU-R BT 601.5 10001 HDTV, 74.25 SMPTE 260M 10010 HDTV, 74.25 SMPTE 274M 10011 HDTV, 74.25 SMPTE 274M 11001 HDTV, 74.25 SMPTE 274M 11010 HDTV, 74.25 ...
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Pin # SEL[5] in each register indicates whether the port pin is input or output. The port pin will be an input when this bit is set and an output when reset. Input-only functions may not be configured ...
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Test Pattern Bit 5 Select Word Bits > 1=HD Video Raster Standard 0=SD 1125 Line, 74.25 MHz, 30 Frame Interlaced Component (SMPTE 260M) Ref. Black 1 PLL Path Path. 1 color Bars 1 1125 Line, 74.25 MHz, 30 ...
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Test Pattern Bit 5 Select Word Bits > 525 Line, 30 Frame, 27 MHz, NTSC 4x3 (SMPTE 125M) Ref. Black 0 PLL Path Path. 0 color Bars (SD 0 BIST) 625 Line, 25 Frame, 27 MHz, PAL 4x3 ...
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TABLE 6. I/O Configuration Register Addresses for Control Register Functions Register Bit [5] [4] reserved Flag Error Flag Error 0 0 ANC Flag 0 0 Error CRC Error 0 0 (SD/HD) Addresses x05h through ...
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Register Bit [5] [4] Dither Enable 1 0 FIFO Insert 1 0 Enable Bit Address Pin # SEL [n] [3] [2] [ Power-On I/P or O/P Status [0] 1 Input 1 Input www.national.com ...
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Pin Descriptions Pin Name 1 V DDPLLD 2 V SSPLLD 3 IO0 4 IO1 5 DV0 6 DV1 7 DV2 8 DV3 9 DV4 10 V SSD 11 DV5 12 DV6 13 DV7 14 DV8 15 DV9 16 V DDD ...
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Pin Name 49 RD/WR 50 ANC/CTRL 51 V DDSD 52 R PRE REF 53 R LVL REF 54 V SSSD 55 V SSSD 56 SDO 57 V DDLS 58 SDO 59 V SSLS 60 V DDZ 61 V SSPLLA 62 ...
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Application Information Complete details for the SD130ASM evaluation PCB are available on National’s WEB site. This circuit demonstrates the capabilities of the LMH0030 and allows its evaluation in a native configuration. An assembled demonstration board kit, part number SD130EVK, complete ...
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... Physical Dimensions inches (millimeters) unless otherwise noted 64-Pin TQPF Order Number LMH0030VS NS Package Number VEC-64A 29 www.national.com ...
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