LP2995MR National Semiconductor, LP2995MR Datasheet - Page 3

• Manufacturer Part Number: LP2995MR
• Description: Voltage Regulator IC
• Manufacturer: National Semiconductor

Specifications of LP2995MR

• No. Of Pins: 8
• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 5V
• Leaded Process Compatible: No
• Package / Case: 8-PSOP
• Output Current Max: 1500A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

V
VOS
∆V
Z
Z
I
q
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Electrical Characteristics
type apply over the full Operating Temperature Range (T
AVIN = PVIN = 2.5V, VDDQ = 2.5V (Note 6).
Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating range indicates conditions for which the device is
intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions see Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed
test conditions.
Note 2: V
Note 3: Load regulation is tested by using a 10ms current pulse and measuring V
Note 4: Quiescent current defined as the current flow into AVIN.
Note 5: At elevated temperatures, devices must be derated based on thermal resistance. The device in the SO-8 package must be derated at θ
junction to ambient with no heat sink. The device in the LLP-16 must be derated at θ
Note 6: Limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control
(SQC) methods. The limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Note 7: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.
REF
VREF
VDDQ
PVIN, AVIN, VDDQ to GND
Storage Temp. Range
Junction Temperature
PSOP-8 Thermal Resistance (θ
SO-8 Thermal Resistance (θ
TT
Symbol
VTT
/V
TT
TT
offset is the voltage measurement defined as V
V
V
Load Regulation
(Note 3)
V
VDDQ Input Impedance
Quiescent Current
REF
TT
REF
Output Voltage Offset
Voltage
Output Impedance
Parameter
JA
)
JA
)
−65˚C to +150˚C
Specifications with standard typeface are for T
−0.3V to +6V
(Note 1)
TT
I
I
(Note 2)
I
I
I
I
(Note 4)
REF_OUT
OUT
OUT
OUT
REF
OUT
subtracted from V
151˚C/W
43˚C/W
= −5µA to +5µA
= 0A
= 0 to 1.5A
= 0 to −1.5A
= 0A
150˚C
Conditions
= 0mA
J
= 0˚C to +125˚C). Unless otherwise specified,
3
REF
TT
.
.
JA
Operating Range
LLP-16 Thermal Resistance (θ
Lead Temperature (Soldering, 10 sec)
ESD Rating (Note 7)
Junction Temp. Range (Note 5)
AVIN to GND
PVIN to GND
= 51˚ C/W junction to ambient.
1.21
Min
−15
−20
J
= 25˚C and limits in boldface
1.235
−0.5
Typ
100
250
0.5
0
5
JA
)
Max
1.26
400
15
20
0˚C to +125˚C
2.2V to AVIN
2.2V to 5.5V
JA
www.national.com
= 151˚ C/W
51˚C/W
Units
260˚C
mV
kΩ
kΩ
µA
%
V
1kV