PIC16F767-E/ML Microchip Technology, PIC16F767-E/ML Datasheet - Page 103

• Manufacturer Part Number: PIC16F767-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F767-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.3.8
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from Sleep. After the device returns to
normal mode, the module will continue to transmit/
receive data.
In Slave mode, the SPI Transmit/Receive Shift register
operates asynchronously to the device. This allows the
device to be placed in Sleep mode and data to be
shifted into the SPI Transmit/Receive Shift register.
When all 8 bits have been received, the MSSP interrupt
flag bit will be set and if enabled, will wake the device
from Sleep.
10.3.9
A Reset disables the MSSP module and terminates the
current transfer.
TABLE 10-2:
 2004 Microchip Technology Inc.
INTCON
PIR1
PIE1
TRISC
SSPBUF
SSPCON
TRISA
SSPSTAT
Legend:
Note 1:
Name
GIE/GIEH PEIE/GIEL
PORTC Data Direction Register
Synchronous Serial Port Receive Buffer/Transmit Register
PORTA Data Direction Register
x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI™ mode.
The PSPIF and PSPIE bits are reserved on 28-pin devices; always maintain these bits clear.
SLEEP OPERATION
EFFECTS OF A RESET
PSPIF
PSPIE
WCOL
Bit 7
SMP
(1)
(1)
REGISTERS ASSOCIATED WITH SPI™ OPERATION
SSPOV
ADIE
Bit 6
ADIF
CKE
TMR0IE
SSPEN
RCIE
RCIF
Bit 5
D/A
INT0IE
TXIE
Bit 4
TXIF
CKP
P
SSPM3
SSPIF
SSPIE
RBIE
Bit 3
S
10.3.10
Table 10-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 10-1:
There is also an SMP bit which controls when the data
is sampled.
TMR0IF
CCP1IE
CCP1IF
SSPM2
Mode Terminology
Bit 2
R/W
Standard SPI™
0, 0
0, 1
1, 0
1, 1
TMR2IF
TMR2IE
SSPM1
INT0IF
BUS MODE COMPATIBILITY
Bit 1
UA
SPI™ BUS MODES
TMR1IF
TMR1IE
SSPM0
RBIF
Bit 0
BF
PIC16F7X7
CKP
Control Bits State
0000 000x 0000 000u
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
POR, BOR
0
0
1
1
Value on
DS30498C-page 101
Value on
CKE
all other
Resets
1
0
1
0