PIC16F767-E/ML Microchip Technology, PIC16F767-E/ML Datasheet - Page 271

• Manufacturer Part Number: PIC16F767-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F767-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SS ....................................................................................... 93
SSPBUF.............................................................................. 98
SSPIF Bit ............................................................................ 25
SSPOV.............................................................................. 123
SSPOV Status Flag .......................................................... 123
SSPSR ................................................................................ 98
SSPSTAT Register
Stack ................................................................................... 29
Status Register
Synchronous Serial Port
T
T1CKPS0 Bit ....................................................................... 78
T1CKPS1 Bit ....................................................................... 78
T1OSCEN Bit ...................................................................... 78
T1SYNC Bit......................................................................... 78
T2CKPS0 Bit ....................................................................... 86
T2CKPS1 Bit ....................................................................... 86
T
Timer0 ................................................................................. 73
Timer1 ................................................................................. 77
Timer2 ................................................................................. 85
 2004 Microchip Technology Inc.
AD
.................................................................................... 157
R/W Bit...................................................................... 107
Overflows .................................................................... 29
Underflows .................................................................. 29
C Bit ............................................................................ 21
DC Bit.......................................................................... 21
IRP Bit......................................................................... 21
PD Bit.................................................................. 21, 172
TO Bit.................................................................. 21, 172
Z Bit............................................................................. 21
Associated Registers .................................................. 76
Clock Source Edge Select (T0SE Bit)......................... 22
Clock Source Select (T0CS Bit).................................. 22
Interrupt....................................................................... 73
Operation .................................................................... 73
Overflow Enable (TMR0IE Bit).................................... 23
Overflow Flag (TMR0IF Bit) ...................................... 185
Overflow Interrupt ..................................................... 185
Prescaler..................................................................... 74
T0CKI.......................................................................... 74
Use with External Clock .............................................. 74
Associated Registers .................................................. 83
Asynchronous Counter Mode ..................................... 80
Capacitor Selection..................................................... 81
Counter Operation ...................................................... 79
Operation .................................................................... 77
Operation in Synchronized
Operation in Timer Mode ............................................ 79
Oscillator ..................................................................... 81
Oscillator Layout Considerations ................................ 81
Prescaler..................................................................... 82
Resetting Timer1 Register Pair................................... 82
Resetting Using a CCP Trigger Output....................... 81
Use as a Real-Time Clock .......................................... 82
Associated Registers .................................................. 86
Output ......................................................................... 85
Postscaler ................................................................... 85
Prescaler..................................................................... 85
Prescaler and Postscaler ............................................ 85
Interrupt Flag Bit (SSPIF)........................................... 25
Reading and Writing ........................................... 80
Counter Mode ..................................................... 79
Timing Diagrams
A/D Conversion ........................................................ 236
Acknowledge Sequence ........................................... 126
Asynchronous Master Transmission ........................ 139
Asynchronous Master Transmission
Asynchronous Reception.......................................... 140
Asynchronous Reception with
Asynchronous Reception with
AUSART Synchronous Receive
AUSART Synchronous Transmission
Baud Rate Generator with Clock Arbitration............. 120
BRG Reset Due to SDA Arbitration
Brown-out Reset....................................................... 225
Bus Collision During a Repeated
Bus Collision During a Repeated
Bus Collision During a Stop Condition
Bus Collision During a Stop Condition
Bus Collision During Start Condition
Bus Collision During Start Condition
Bus Collision for Transmit and
Capture/Compare/PWM
CLKO and I/O ........................................................... 224
Clock Synchronization .............................................. 113
External Clock .......................................................... 223
Fail-Safe Clock Monitor ............................................ 189
First Start Bit ............................................................. 121
I
I
I
I
I
I
I
I
I
I
Low-Voltage Detect .................................................. 177
LP Clock to Primary System Clock after
LP Clock to Primary System Clock after
Parallel Slave Port .................................................... 228
Parallel Slave Port Read ............................................ 71
2
2
2
2
2
2
2
2
2
2
C Bus Data............................................................. 232
C Bus Start/Stop Bits ............................................. 231
C Master Mode (Reception,
C Master Mode (Transmission,
C Slave Mode (Transmission,
C Slave Mode (Transmission,
C Slave Mode with SEN = 0 (Reception,
C Slave Mode with SEN = 0 (Reception,
C Slave Mode with SEN = 1 (Reception,
C Slave Mode with SEN = 1 (Reception,
(Back to Back) .................................................. 139
Address Byte First ............................................ 143
Address Detect ................................................. 143
(Master/Slave) .................................................. 234
(Master/Slave) .................................................. 234
During Start Condition ...................................... 129
Start Condition (Case 1) ................................... 130
Start Condition (Case 2) ................................... 130
(Case 1)............................................................ 131
(Case 2)............................................................ 131
(SCL = 0) .......................................................... 129
(SDA Only) ....................................................... 128
Acknowledge .................................................... 127
(CCP1 and CCP2) ............................................ 227
7-bit Address) ................................................... 125
7 or 10-bit Address) .......................................... 124
10-bit Address) ................................................. 111
7-bit Address) ................................................... 109
10-bit Address) ................................................. 110
7-bit Address) ................................................... 108
10-bit Address) ................................................. 115
7-bit Address) ................................................... 114
Reset (EC, RC, INTRC)...................................... 46
Reset (HS, XT, LP)............................................. 45
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