PIC16F876AT-I/SS Microchip Technology, PIC16F876AT-I/SS Datasheet - Page 111

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PIC16F876AT-I/SS

Manufacturer Part Number
PIC16F876AT-I/SS
Description
28 PIN, 14KB ENH FLASH, 368 RAM, 22 I/O,
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F876AT-I/SS

Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
9.4.17.3
Bus collision occurs during a Stop condition if:
a)
b)
FIGURE 9-31:
FIGURE 9-32:
 2003 Microchip Technology Inc.
After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
SSPIF
BCLIF
SSPIF
BCLIF
SDA
PEN
SCL
SDA
PEN
SCL
P
Bus Collision During a Stop
Condition
P
BUS COLLISION DURING A STOP CONDITION (CASE 1)
BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDA asserted low
Assert SDA
T
BRG
T
BRG
T
T
BRG
BRG
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD<6:0>
and counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 9-31). If the SCL pin is sampled
low before SDA is allowed to float high, a bus collision
occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 9-32).
SCL goes low before SDA goes high,
set BCLIF
T
BRG
T
BRG
PIC16F87XA
SDA sampled
low after T
set BCLIF
DS39582B-page 109
‘0’
‘0’
‘0’
‘0’
BRG
,

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