PIC16F876AT-I/SS Microchip Technology, PIC16F876AT-I/SS Datasheet - Page 30

• Manufacturer Part Number: PIC16F876AT-I/SS
• Description: 28 PIN, 14KB ENH FLASH, 368 RAM, 22 I/O,
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F876AT-I/SS

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F87XA
2.2.2.7
The PIR2 register contains the flag bits for the CCP2
interrupt, the SSP bus collision interrupt, EEPROM
write operation interrupt and the comparator interrupt.
REGISTER 2-7:
DS39582B-page 28
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-1
bit 0
PIR2 Register
PIR2 REGISTER (ADDRESS 0Dh)
Unimplemented: Read as ‘0’
CMIF: Comparator Interrupt Flag bit
1 = The comparator input has changed (must be cleared in software)
0 = The comparator input has not changed
Unimplemented: Read as ‘0’
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred in the SSP when configured for I
0 = No bus collision has occurred
Unimplemented: Read as ‘0’
CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused.
Legend:
R = Readable bit
- n = Value at POR
bit 7
U-0
—
R/W-0
CMIF
U-0
—
W = Writable bit
‘1’ = Bit is set
R/W-0
EEIF
Note:
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
BCLIF
Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to
enabling an interrupt.
 2003 Microchip Technology Inc.
U-0
2
—
C Master mode
x = Bit is unknown
U-0
—
CCP2IF
R/W-0
bit 0