PIC16F884-E/P Microchip Technology, PIC16F884-E/P Datasheet - Page 190

• Manufacturer Part Number: PIC16F884-E/P
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,DIP,40PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F884-E/P

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F882/883/884/886/887
13.3.6
In Master mode, all module clocks are halted, and the
transmission/reception will remain in that state until the
device wakes from Sleep. After the device returns to
normal mode, the module will continue to transmit/
receive data.
In Slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the
device to be placed in Sleep mode and data to be
shifted into the SPI transmit/receive shift register.
When all eight bits have been received, the MSSP
interrupt flag bit will be set and, if enabled, will wake the
device from Sleep.
13.3.7
A Reset disables the MSSP module and terminates the
current transfer.
TABLE 13-2:
DS41291F-page 188
INTCON
PIE1
PIR1
SSPBUF
SSPCON
SSPSTAT
TRISA
TRISC
Legend:
Note
Name
1:
Synchronous Serial Port Receive Buffer/Transmit Register
Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other oscillator modes, they are disabled and
read ‘0’.
GIE/GIEH
x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
TRISA7
TRISC7
SLEEP OPERATION
EFFECTS OF A RESET
WCOL
Bit 7
SMP
—
—
REGISTERS ASSOCIATED WITH SPI OPERATION
PEIE/GIEL
SSPOV
TRISA6
TRISC6
ADIE
ADIF
Bit 6
CKE
TRISA5
TRISC5
SSPEN
RCIE
RCIF
Bit 5
T0IE
D/A
TRISC4
TRISA4
Bit 4
INTE
TXIE
TXIF
CKP
P
TRISA3
TRISC3
SSPM3
SSPIE
SSPIF
RBIE
Bit 3
S
CCP1IE
CCP1IF
TRISA2
TRISC2
13.3.8
Table 13-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 13-1:
There is also a SMP bit that controls when the data will
be sampled.
SSPM2
Bit 2
T0IF
R/W
Standard SPI Mode
Terminology
0, 0
0, 1
1, 0
1, 1
TMR2IE
TMR2IF
TRISA1
TRISC1
SSPM1
BUS MODE COMPATIBILITY
Bit 1
INTF
UA
SPI BUS MODES
TMR1IE
TMR1IF
SSPM0
TRISA0
TRISC0
RBIF
Bit 0
BF
© 2009 Microchip Technology Inc.
CKP
Control Bits State
0000 000x
0000 0000
-000 0000
xxxx xxxx
0000 0000
0000 0000
1111 1111
1111 1111
0
0
1
1
POR, BOR
Value on
0000 000u
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
1111 1111
1111 1111
CKE
Value on
RESETS
all other
1
0
1
0