PIC16F884-E/P Microchip Technology, PIC16F884-E/P Datasheet - Page 319

• Manufacturer Part Number: PIC16F884-E/P
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,DIP,40PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F884-E/P

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

EUSART ........................................................................... 151
F
Fail-Safe Clock Monitor....................................................... 71
Firmware Instructions........................................................ 231
Flash Program Memory .................................................... 111
Fuses. See Configuration Bits
G
General Call Address Support .......................................... 192
General Purpose Register File............................................ 22
I
I
I
I
I
© 2009 Microchip Technology Inc.
2
2
2
2
C (MSSP Module)
C Master Mode Reception.............................................. 198
C Master Mode Repeated Start Condition Timing.......... 197
C Module
Associated Registers
Asynchronous Mode ................................................. 153
Baud Rate Generator (BRG)
Synchronous Master Mode ............................... 171, 175
Synchronous Slave Mode
Fail-Safe Condition Clearing ....................................... 71
Fail-Safe Detection ..................................................... 71
Fail-Safe Operation..................................................... 71
Reset or Wake-up from Sleep..................................... 71
Writing....................................................................... 117
ACK Pulse......................................................... 189, 190
Addressing ................................................................ 190
Read/Write Bit Information (R/W Bit) ........................ 190
Reception.................................................................. 190
Serial Clock (RC3/SCK/SCL).................................... 190
Slave Mode ............................................................... 189
Transmission............................................................. 190
Acknowledge Sequence Timing................................ 201
Baud Rate Generator................................................ 195
Baud Rate Generator........................................ 163
12-bit Break Transmit and Receive .................. 169
Associated Registers
Auto-Wake-up on Break ................................... 168
Baud Rate Generator (BRG) ............................ 163
Clock Accuracy ................................................. 160
Receiver............................................................ 156
Setting up 9-bit Mode with Address Detect....... 158
Transmitter........................................................ 153
Auto Baud Rate Detect ..................................... 167
Baud Rate Error, Calculating ............................ 163
Baud Rates, Asynchronous Modes .................. 164
Formulas ........................................................... 163
High Baud Rate Select (BRGH Bit) .................. 163
Associated Registers
Reception.......................................................... 173
Requirements, Synchronous Receive .............. 266
Requirements, Synchronous Transmission ...... 266
Timing Diagram, Synchronous Receive ........... 266
Timing Diagram, Synchronous Transmission ... 266
Transmission .................................................... 171
Associated Registers
Reception.......................................................... 176
Transmission .................................................... 175
Receive..................................................... 159
Transmit.................................................... 155
Receive..................................................... 174
Transmit.................................................... 172
Receive..................................................... 176
Transmit.................................................... 175
PIC16F882/883/884/886/887
ID Locations...................................................................... 227
In-Circuit Debugger........................................................... 229
In-Circuit Serial Programming (ICSP)............................... 227
Indirect Addressing, INDF and FSR registers..................... 37
Instruction Format............................................................. 231
Instruction Set................................................................... 231
BRG Block Diagram ................................................. 195
BRG Reset Due to SDA Arbitration During
BRG Timing .............................................................. 195
Bus Collision
Bus Collision timing .................................................. 203
Clock Arbitration ....................................................... 202
Clock Arbitration Timing (Master Transmit) .............. 202
Effect of a Reset ....................................................... 202
General Call Address Support .................................. 192
Master Mode............................................................. 193
Master Mode 7-bit Reception Timing........................ 200
Master Mode Operation............................................ 194
Master Mode Start Condition Timing ........................ 196
Master Mode Support ............................................... 193
Master Mode Transmission ...................................... 198
Master Mode Transmit Sequence ............................ 194
Multi-Master Mode.................................................... 203
Repeat Start Condition Timing Waveform ................ 197
Sleep Operation........................................................ 202
Stop Condition Receive or Transmit Timing ............. 202
Stop Condition Timing .............................................. 201
Waveforms for 7-bit Reception ................................. 191
Waveforms for 7-bit Transmission............................ 191
ADDLW..................................................................... 233
ADDWF .................................................................... 233
ANDLW..................................................................... 233
ANDWF .................................................................... 233
BCF .......................................................................... 233
BSF........................................................................... 233
BTFSC...................................................................... 233
BTFSS ...................................................................... 234
CALL......................................................................... 234
CLRF ........................................................................ 234
CLRW ....................................................................... 234
CLRWDT .................................................................. 234
COMF ....................................................................... 234
DECF........................................................................ 234
DECFSZ ................................................................... 235
GOTO ....................................................................... 235
INCF ......................................................................... 235
INCFSZ..................................................................... 235
IORLW ...................................................................... 235
IORWF...................................................................... 235
MOVF ....................................................................... 236
MOVLW .................................................................... 236
MOVWF.................................................................... 236
NOP.......................................................................... 236
RETFIE..................................................................... 237
RETLW ..................................................................... 237
Start Condition.................................................. 205
Acknowledge .................................................... 203
Repeated Start Condition ................................. 206
Repeated Start Condition Timing (Case1)........ 206
Repeated Start Condition Timing (Case2)........ 206
Start Condition.................................................. 204
Start Condition Timing .............................. 204, 205
Stop Condition .................................................. 207
Stop Condition Timing (Case 1) ....................... 207
Stop Condition Timing (Case 2) ....................... 207
DS41291F-page 317