TLE4941-1C Infineon Technologies, TLE4941-1C Datasheet - Page 5
Manufacturer Part Number
IC HALL EFFECT SENSOR PSSO-2-2
Specifications of TLE4941-1C
Voltage - Supply
4.5 V ~ 20 V
Current - Supply
Digital, PWM (Current)
-40°C ~ 150°C
Package / Case
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output (max)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
The differential hall sensor IC detects the motion of ferromagnetic and permanent
magnet structures by measuring the differential flux density of the magnetic field. To
detect the motion of ferromagnetic objects the magnetic field must be provided by a back
biasing permanent magnet. Either south or north pole of the magnet can be attached to
the rear unmarked side of the IC package.
Magnetic offsets of up to ± 20 mT and device offsets are cancelled by a self-calibration
algorithm. Only a few transitions are necessary for self-calibration. After the initial
calibration sequence switching occurs when the input signal is crossing the arithmetic
mean of its max. and min. value (e.g. zero-crossing for sinusoidal signals).
The ON and OFF state of the IC are indicated by High and Low current consumption.
The circuit is supplied internally by a 3 V voltage regulator. An on-chip oscillator serves
as clock generator for the digital part of the circuit.
TLE4941 signal path is comprised of a pair of hall probes, spaced at 2.5 mm, a
differential amplifier including a noise-limiting low-pass filter and a comparator feeding a
switched current output stage. In addition an offset cancellation feedback loop is
provided by a signal-tracking A/D converter, a digital signal processor (DSP) and an
offset cancellation D/A converter.
During the startup phase (un-calibrated mode) the output is disabled (
The differential input signal is digitized in the speed A/D converter and fed into the DSP.
The minimum and maximum values of the input signal are extracted and their
corresponding arithmetic mean value is calculated. The offset of this mean value is
determined and fed into the offset cancellation DAC.
After successful correction of the offset, the output switching is enabled.
In running mode (calibrated mode) the offset correction algorithm of the DSP is switched
into a low-jitter mode, avoiding oscillation of the offset DAC LSB. Switching occurs at
zero-crossing. It is only affected by the (small) remaining offset of the comparator and by
the remaining propagation delay time of the signal path, mainly determined by the noise-
limiting filter. Signals below a defined threshold
are not detected to avoid
unwanted parasitic switching.
Pure tin covering (green lead plating) is used. Leadframe material is Wieland K62 (UNS:
C18090) and contains CuSn1CrNiTi. Product is RoHS (restriction of hazardous
substances) compliant when marked with letter G in front or after the data code marking
and may contain a data matrix code on the rear side of the package (see also information
note 136/03). Please refer to your Key account team or regional sales if you need further