ADNK-7633 Avago Technologies US Inc., ADNK-7633 Datasheet - Page 13

• Manufacturer Part Number: ADNK-7633
• Description: A7630 Reference Design Kit
• Manufacturer: Avago Technologies US Inc.
• Type: Transceiver, Bluetooth 2.1+EDRr

Specifications of ADNK-7633

• Frequency: 2.4GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCB Layout Requirements:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Keep ANTN and ANTP traces (from IC to antenna)
*Disclaimer: All designers and manufacturers of this design must assure that they have all necessary intellectual property rights.
Recommended to use 4-layer PCB board, with second
layer as GND plane and third layer as power plane.
Cut the copper beneath the antenna pattern on the
GND plane, power layer and the bottom layer; no signal
line is allowed beneath the antenna pattern at all of
the layers. Antenna pattern is highly recommended
to be located at one of the board edges, furthest away
from palm coverage.
Keeping any metallic objects (eg. Battery terminal
plates) at least 15mm away from the antenna as this
is the distance of the near field for electromagnetic
field.
Power lines should be thick and short. Big via holes
are recommended whenever needed.
C37 and C34, C55 and C54, C57 and C56, should be
placed as near as possible to pin 5, pin 4 and pin 56
respectively for effective decoupling.
C39 and C38, C61 and C59, C58 and C40, should be
placed as near as possible to pin 57, pin 2 and pin 8
respectively for effective decoupling.
The ground pad beneath the centre of the ADNS-7630
QFN package should have sufficient via holes down
to the same ground plane (2nd layer of the PCB). Use
solder mask to prevent any unwanted short circuit.
Prepare necessary area of solder pads only.
Components connected to CPOUT (pin 3) and VCTRL
(pin 55) must as close as possible to ADNS-7630 IC.
It is recommended to complete the loop within the
same PCB layer.
Keep sufficient clearance between RF Trace class_1
(from pin ANTN to Antenna) and Ground copper
(if applicable) on the top side 3 times larger than
h (height of top layer to GND layer); the same
requirement is needed for RF Trace class_2 (from pin
ANTP to Antenna) and Ground copper (if applicable).
Keep a clearance between VDD_RX (pin 5) and ANTN
(pin 6) traces, as well as between ANTP (pin 7) and
VDD_IF (pin 8) traces.
parallel, short and as straight as possible without
many curves. Recommended to have differential
impedance between ANTN and ANTP to be 100Ω, and
unbalanced trace (from C4 to ANTENNA) impedance
controlled to 50Ω.
11. Keep a clearance between antenna and ground.
12. Ensure large grounding plane and more via holes at
13. Components connected to the pins below MUST
14. C17 must be as close as possible to the ADNS-7630
15. All separate AGND, GND_RF and GND paths MUST be
16. All caps MUST be as close to the power pins as possible,
17. Frequency tolerance of crystal oscillator should follow
18. Ceramic non-polarity caps and tantalum polarity
19. Capacitors connected to VDD3 MUST have less than
20. It is optional but highly recommended for customers
21. Ensure that no component is placed at the lens
22. Add an optional π-type filter at antenna circuit to
GND (pin 27, pin 32 and pin 33) down to the ground
plane (2nd layer of the PCB).
complete the loop within the same PCB layer (no
usage via holes allowed).
a. BIASVAR (pin 54)
b. REGO (pin 36)
c. VDD3 (pin 31, 35, 50)
IC.
via down to the same ground plane (2nd layer of the
PCB). Ensure large grounding plane on the PCB layout
for better performance on ESD and EFTB.
with the smaller capacitors nearer to the ADNS-7630
IC.
the specification of +/- 20PPM. Recommended to use
TST TZ0683B 12MHz crystal. Crystal should be placed
less than 10mm (must not be more than 15mm) from
ADNS-7630 XTALIN and XTALOUT pins.
capacitors are recommended.
0.2Ω ESR.
to route some signals to a 2mm pin header (only to
be soldered when troubleshooting is needed) on
the mouse board to ease Avago’s technical support
in future. Refer to Design Guide – Hardware for more
information.
clearance area as shown in Figure 4 so that the lens is
interlocked to the PCB at the correct vertical height.
suppress 4.8G/7.2GHz harmonics.