ADNS-5050 Avago Technologies US Inc., ADNS-5050 Datasheet - Page 15

• Manufacturer Part Number: ADNS-5050
• Description: 8 DIP SFF Navigation Sensor
• Manufacturer: Avago Technologies US Inc.

Specifications of ADNS-5050

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 516-2261; ADNS-5050

Motion Burst Timing
Burst Mode Operation
Burst mode is a special serial port operation mode that may
be used to reduce the serial transaction time for a motion
read. The speed improvement is achieved by continuous
data clocking to or from multiple registers without the
need to specify the register address, and by not requiring
the normal delay period between data bytes.
Burst mode is activated by reading the Motion_Burst
register. The ADNS-5050 will respond with the contents
of the Delta_X, Delta_Y, SQUAL, Shutter_Upper, Shutter_
Lower, Maximum_Pixel and Pixel_Sum registers in that
order. The burst transaction can be terminated anywhere
in the sequence after the Delta_X value by bringing the
NCS pin high. After sending the register address, the
micro-controller must wait tSRAD and then begin reading
data. All data bits can be read with no delay between
bytes by driving SCLK at the normal rate. The data are
latched into the output buffer after the last address bit
is received. After the burst transmission is complete, the
micro-controller must raise the NCS line for at least tBEXIT
to terminate burst mode. The serial port is not available
for use until it is reset with NCS, even for a second burst
transmission.
Avago Technologies highly recommends the usage of burst
mode operation in optical mouse sensor design applica-
tions.
Notes on Power-up and Reset
The ADNS-5050 does not perform an internal power up
self-reset. There are two ways to reset the chip, either
assert low NRESET pin or by writing 0x5a to register 0x3a.
A full reset will thus be executed. Any register settings
must then be reloaded.
15
SCLK
MOTION_BURST REGISTER ADDRESS
FIRST READ OPERATION
READ FIRST BYTE
t
SRAD
READ SECOND BYTE
During power-up there will be a period of time after the
power supply is high but before any clocks are available.
The table below shows the state of the various pins during
power-up and reset.
State of Signal Pins After V
Pin
NCS
SDIO
SCLK
XY_LED
Notes on Power Down
The ADNS-5050 can be set in Power Down mode by setting
bit 1 of register 0x0d. In addition, the SPI port should not
be accessed during power down. (Other ICs on the same
SPI bus can be accessed, as long as the sensor’s NCS pin is
not asserted.) The table below shows the state of various
pins during power down. There are 2 ways to exit power
down, either assert low NRESET pin or by writing 0x5a to
Register 0x3a. A full reset will thus be executed. Wait for
t
must then be reloaded.
*
NOTE: There is long wakeup time from power down.
WAKEUP
Pin
NRESET
NCS
SDIO
SCLK
XY_LED
NCS pin must be held to 1(high) if SPI bus is shared with other devices.
It can be in either state if the sensor is the only device in addition to
the controller microprocessor.
before accessing the SPI port. Any register settings
READ THIRD BYTE
During Reset
Ignored
Ignored
Ignored
Hi-Z
Power Down Active
Functional
Functional*
Functional*
Functional*
Power Down
DD
is Valid
• • •
• • •
After Reset
Functional
Depends on NCS
Depends on NCS
Functional