S1D15206F00A200 Epson, S1D15206F00A200 Datasheet - Page 348

• Manufacturer Part Number: S1D15206F00A200
• Description: LCD Drivers LCD DRIVER
• Manufacturer: Epson

Specifications of S1D15206F00A200

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6. FUNCTION DESCRIPTION
Enable Shift Register
The order of the display data latched is reversed by the
SHL input.
Enable Control and Data Control
If the enable signal is disabled (EIO = HIGH), the
internal clock signal and the data bus are fixed to LOW.
This is a power-save mode.
To use multiple segment drivers, connect in cascade
format the EIO pin of each driver, and connect the EIO
pin of the first driver to the “V
The enable control circuit automatically detects when the
80 bit data has been read and automatically transfers the
enable signal. As a result, a control signal by a control
LSI is not necessary.
Display RAM
This is a static RAM (200 80 bits) that stores the LCD
data.
The display RAM data (80 bit) for the low address is read
out to the latch with the trailing edge of the LP signal. In
addition, with the trailing edge of the LP signal, the
contents of the data register is moved to the write register.
The contents of the write register are then written in the
display RAM area for the low address. The low address
is then incremented.
If the XSCL signal does not come in after the trailing
edge of the LP signal, the mode is changed to the self-
refresh mode. The write register does not write data in
the display RAM and the low address is incremented.
The mode is then changed to the read out mode to read the
next line.
Low Address Counter Decoder
This selects a line of the display RAM in sequence. This
decoder catches the HIGH of the YD signal at the trailing
edge of the LP signal, and resets the low address counter.
It then initialize the selected address of the display RAM.
In a normal operation, the decoder is incremented after
the writing operation into the display RAM. (The writing
operation is caused by the trailing edge of the LP signal.)
In the self-refresh mode, the decoder is incremented
without the writing operation into the display RAM.
S1D15700 Series
9–6
SS
” pin.
EPSON
Data Register
This 80 bit register controls the write operation into the
display RAM. The data is written in the display RAM
with the trailing edge of the LP signal. In the self-refresh
mode, the data is not written in the display RAM.
Control Circuit
The control circuit detects the self-refresh mode, allows
the write register to write the data into the display RAM,
and controls and low address count signal.
Latch
This reads the 80 bit data for the low address of the
display RAM with the trailing edge of the LP signal, and
sends the output signal to the level shifter.
Level Shifter
This is the level interface circuit that converts the signal
voltage level from V
power).
LCD Driver
The LCD driver outputs the LCD driver voltage.
The table below shows the relationship between the
display signals (D
(FR) and the segment output voltage.
DOFF
HIGH
LOW
D
HIGH
LOW
0
—
– D
3
DD
– D
3
– V
0
), LCD AC-drive wave form
SS
HIGH
HIGH
LOW
LOW
FR
—
to V
DD
X Output Voltage
– V
EE
(LCD driver
V
V
V
V
V
0
5
2
3
0
Rev. 3.0