CORR-8BIT-PM-U2 Lattice, CORR-8BIT-PM-U2 Datasheet - Page 7

• Manufacturer Part Number: CORR-8BIT-PM-U2
• Description: Development Software Correlator IP Core User Config
• Manufacturer: Lattice

Specifications of CORR-8BIT-PM-U2

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 6. Example Coefficient Sequences Written in Coefficient Memory
In configurations where the number of taps is not a power of 2, the coefficient sequences will need to be padded
with zeros so that all coefficient sequences written to the Coefficient Memory are a power of 2 long. This is
because the Coefficient and Tap Memories must be divided up evenly into sections representing the individual
channels and coefficient sequences. In the example above, if the number of taps were less than 16, the coefficients
would still be written into memory the same way except that padding zeros would be added before the MSB. The
padding zeros would be written into memory starting at the MSB of row 3 for coefficient sequence 0.
Correlator and Adder/Accumulator Blocks
The Correlator block performs the multiplication operations in Equations 1 and 2. The coefficients are configured by
the user to be either unsigned or signed. If unsigned, then the binary coefficient values simply represent {1,0} and
the multiplications reduce to either passing the tap values read from memory to the Adder/Accumulator, or passing
a zero value. If the coefficients are signed, then the binary coefficients {1,0} represent values of {+1,-1}. If a tap
value is multiplied by 1, then the Correlator block does nothing other than pass the tap value read from memory to
the Adder/Accumulator. If a tap value is multiplied by -1, then the Correlator block does a two’s complement conver-
sion of the tap value read from memory and passes the result to the Adder/Accumulator, which in turn completes
the summation of the correlation sequence to generate the final result.
Decimation
The Correlator IP core allows the input data to be oversampled from two to eight times the normal sampling rate.
The OS_FACTOR parameter should be set to the correct oversampling rate. When this is done, the core will auto-
matically decimate the amount of data which is included in the correlation operations by the correct amount. For
example, if the number of taps is eight and an oversampling rate of two is chosen, then the circuit will correlate the
eight coefficient values with the newest input tap data value and the odd numbered tap data values from the past
15 “old” data values. The correlation will look like this:
The number of data values stored in Tap Memory for a given channel becomes [OS_FACTOR*NUM_TAP], or in
this case 16. The number of coefficients per channel is still equal to NUM_TAP.
r = d1c1 + d3c2 + d5c3 + d7c4 + d9c5 + d11c6 + d13c7 + d15c8
Upper Locations
of EBR (Unused
in this Example)
Coefficient
Sequence 1
Coefficient
Sequence 0
Row 7
Row 6
Row 5
Row 4
Row 3
Row 2
Row 1
Row 0
7
0
0
1
0
1
0
1
1
MWIDTH wide
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
1
0
0
0
0
1
0
Correlator IP Core
(4)