CorePCI Eval Board Actel, CorePCI Eval Board Datasheet - Page 24

• Manufacturer Part Number: CorePCI Eval Board
• Description: MCU, MPU & DSP Development Tools CorePCI v5.41
• Manufacturer: Actel

Specifications of CorePCI Eval Board

• Processor To Be Evaluated: SX-A device
• Interface Type: RS-232

In the case of a PCI read, the backend must prefetch the
memory data in order to ensure continuity on long
bursts. If prefetching causes a problem, for example in a
FIFO, the backend logic should shadow the last two data
Notes:
1. When FRAMEn is asserted and the command bus is '0111,' then a write to memory space is indicated.
2. The Target will compare the address to the programmed space set in the memory base address register.
3. If an address hit occurs, then the Target asserts DP_START in cycle 3 and claims the PCI bus by asserting DEVSELn in cycle 4.
4. Data transfer to the backend begins on the rising edge of cycle 7 and continues for each subsequent cycle until the PCI bus ends the
5. The address will increment each cycle following an active RD_BE_NOW.
6. The PCI transaction completes when TRDYn is de-asserted in cycle 9 and completes on the backend in cycle 10.
7. For this case, the PIPE_FULL_CNT is set to "000" (See
Figure 7 • 32-Bit Burst Write with Zero Wait States
2 4
CorePCI v5.41
data transfer.
MEM_ADDRESS
WR_BE_NOW
WR_BE_RDY
MEM_DATA
BARn_CYC
DP_START
DP_DONE
DEVSELn
FRAMEn
WR_CYC
TRDYn
STOPn
IRDYn
PAR
CBE
CLK
AD
1
addr
0111
2
Paddr
3
"Backend Latency Control" on page 31
data0
4
v4.0
Pdata0
byte enables
5
transactions. 32-bit zero-wait-state burst transfers are
shown in
64-bit zero-wait-state burst transfers are shown in
Figure 9 on page 26
add0
6
data1
data0
7
Figure 7 on page 24
data2
data1
add1
Pd1
8
data3
data2
add2
Pd2
9
and
data3
add3
for more information).
Pd3
Figure 10 on page
10
and
11
Figure 8 on page
12
27.
25.