CorePCI-AR Actel, CorePCI-AR Datasheet
CorePCI-AR
Specifications of CorePCI-AR
Related parts for CorePCI-AR
CorePCI-AR Summary of contents
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... Version This datasheet defines the functionality of Version 5.41 for CorePCI. Contents General Description ................................................... 2 CorePCI Device Requirements ................................... 3 Utilization Statistics ................................................... 5 CorePCI IP Functional Block Diagram ....................... 6 Data Transactions ....................................................... 6 I/O Signal Descriptions ............................................... 6 CorePCI Target Function .......................................... 12 CorePCI Master Function ......................................... 17 Master Register Access ............................................. 19 System Timing .......................................................... 22 PCI Target Transactions ............................................ 22 PCI Master Transactions ...
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... CorePCI v5.41 General Description CorePCI connects I/O, memory, and processor subsystem resources to the main system via the PCI bus. CorePCI is intended for use with a wide variety of peripherals where high-performance data transactions are required. Figure 1 on page 2 depicts typical system applications using the baseline IP core. While CorePCI can handle any transfer rate, most applications will operate at zero wait states ...
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... CorePCI Device Requirements Performance requirements and bus size both drive device selection. Table 1 summarizes the device requirements. A typical 64-bit PCI system requires at least 200 I/Os. on page 5 shows typical pin counts. The actual number of I/O pins depends on the user backend interface. The table assumes the complete backend interface is connected to I/O pins rather than internal logic ...
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... CorePCI v5.41 Table 2 • Device Utilization for CorePCI Functions Target Device 32-Bit A54SX16A 54% A54SX16P 54% A54SX32A 27% A54SX72A 13% RT54SX32S 27% RT54SX72S 13% AX125 39% AX250 19% AX500 10% AX1000 4% AX2000 2% RTAX250S 19% RTAX1000S 4% RTAX2000S 2% APA075 40% APA150 20% APA300 15% APA450 10% APA600 6% APA750 4% APA1000 2% A3P125 45% A3P250 22% A3P400 15% A3P600 10% A3P1000 5% A3PE600 10% A3PE1500 3% A3PE3000 ...
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... Table 3. The antifuse column indicates the typical R and C module counts for the SX, SX-A, RTSX-S, and Axcelerator families. The Flash column indicates the tile Table 3 • Utilization Statistics for CorePCI Function 32-Bit Target Controller 64-Bit Target Controller 32-Bit Master Controller 64-Bit Master Controller ...
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... ID, status, control, and the base address registers. The core implements a single function Type 0 configuration space. Data Transactions CorePCI is designed to be fully compliant for all transfer types, including transactions. Burst transfers can operate with either zero, one, or more wait states. Normally, CorePCI will burst data with zero wait states ...
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... IDSEL AD PAR CBE PERRn INTAn REQn GNTn DMA Controller CLK RSTn For a complete list of signal descriptions, refer to Figure 2 • CorePCI Block Diagram Dataphase Address Phase State Machine State Machine Parity and Register File Block Configuration Table 5 on page 8 and Table 6 on page v4 ...
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... CorePCI v5.41 Table 5 • CorePCI Interface Signals * Name Type Description CLK Input 33 MHz or 66 MHz clock input for the PCI core RSTn Input Active LOW asynchronous reset AD Bidirectional Multiplexed 32-bit or 64-bit address and data bus. Valid address is indicated by FRAMEn assertion. CBE Bidirectional Bus command and byte enable information ...
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... Table 6 • CorePCI Backend Interface Signal 1,2 Name Type CLK_OUT Output BAR0_MEM_CYC Output BAR1_CYC Output CONFIG_CYC Output RD_CYC Output WR_CYC Output MEM_DIN Input MEM_DOUT Output MEM_DATA_DEN Output MEM_DATA_DEN64 Output 3 MEM_ADD[N:0] Output DP_START Output DP_START64 DP_DONE Output RD_BE_NOW Output RD_BE_NOW64 RD_BE_RDY Input Notes: 1 ...
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... DMA cycle will be stopped within two data transfers, i. two more data cycles may occur when the signal goes high. If high when CorePCI starts a DMA cycle hold off asserting FRAME and starting the cycle on the PCI bus until STALL_MASTER is deasserted (low) signifying that the back end's data is now ready. This can be used to support backends that take several cycles to become ready ...
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... Table 6 • CorePCI Backend Interface Signal (Continued) 1,2 Name Type BUSY Input EXT_INTn Input CS_CONTROLn Input RD_CONTROLn Input WR_CONTROLn Input CONTROL_ADD[1:0] Input MASTER_BE[3:0] Input MASTER_BE64[3:0] Input Notes: 1. Active LOW signals are designated with a trailing lower-case n. 2. Signals ending in "CYC" become valid as the same cycle DP_START is active and will remain valid throughout the current cycle (until DP_DONE is asserted) ...
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... CorePCI v5.41 CorePCI Target Function CorePCI Target function acts like a slave on the PCI bus. The Target controller monitors the bus and checks for hits to either configuration space or to the address space defined in its base address registers (BARs). When a hit is detected, the Target controller notifies the backend and then acts to control the flow of data between the PCI bus and the backend ...
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... Vendor ID Command Latency Timer Base Address #3 Base Address #4 Base Address #5 CardBus CIS Pointer Subsystem Vendor ID Capabilities Pointer Reserved Interrupt Pin v4.0 CorePCI v5.41 Base Address Register Bit Definitions 16) 16) 7–0 Address 00h 04h Revision ID 08h Cache Line Size ...
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... CorePCI v5.41 Table 9 • Command Register (04h) Bit Type Description 0 RW I/O Space A value of '0' disables the device’s response to I/O space addresses. Set to '0' after reset Memory Space A value of '0' disables the device’s response to memory space addresses. Set to '0' after reset. ...
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... Set to '0' at system reset. This bit is set to '1' by internal logic whenever a parity error, address, or data is detected, regardless of the value of bit 6 in the command register. Note: The RW capability in the status register is restricted to clearing the bit by writing a '1' into the bit location. v4.0 CorePCI v5.41 15 ...
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... CorePCI v5.41 Table 11 • Memory Base Address Register Bit Definition (Locations 10h or 14h) Bit Type Description 0 RO Set to '0' to indicate memory space. 2–1 RO Set to '00' to indicate mapping into any 32-bit address space Set to a '1' Indicating prefetch allowed on reads. 23–4 RO Indicates address space set to all '0's. 31– ...
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... Master Registers There are three registers used to control the function of CorePCI Master. The first register is the 32-bit PCI address register. The second register is the 32-bit RAM or backend address register. These two registers provide the source/destination addressing for all data transfers. A 32- bit control register defines the type, length, and status of a Master transfer ...
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... Writing a '1' to this bit enables the external interrupt signal. Writing a '0' to this bit disables external interrupt support Memory Transfer Width Writing a '1' to this bit enables a 64-bit memory transaction. For 32-bit CorePCI cores, this bit is read-only and is set to a '0'. 15–14 RO Reserved (set to '00'b). ...
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... PCI Address Ram Address DMA Control Register Customization Options CorePCI has a variety of options for user customization. A special package defining a list of variables that allow the user to optimize the core for a particular application is included with the source design files. All of the constants are applicable to the Target+DMA function. For Target+Master functions, the DMA_IN_IO constant is not required ...
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... CorePCI v5.41 Table 22 • CorePCI Customization Constants Constant Type 1 USER_DEVICE_ID Binary 1 USER_VENDOR_ID Binary 1 USER_REVISION_ID Binary 1 USER_BASE_CLASS Binary 1 USER_SUB_CLASS Binary 1 USER_PROGRAM_IF Binary 1 USER_SUBSYSTEM_ID Binary 1 USER_SUBVENDOR_ID Binary BIT_64 Binary 1 MHZ_66 Binary 1 DMA_CNT_EN Binary 2 DMA_IN_IO Binary MADDR_WIDTH Integer 3 BAR1_ENABLE Binary 3 BAR1_IO_MEMORY Binary 3 BAR1_ADDR_WIDTH Integer ...
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... Table 22 • CorePCI Customization Constants (Continued) Constant Type ENABLE_BAR_OVERFLOW Binary EXPORT_CLOCK_OUT Binary Notes: 1. Not applicable in Target-only core. 2. Only applicable in Target+DMA core. 3. Not applicable in Master-only core. Description When ENABLE_BAR_OVERFLOW is set the core will force a disconnect at the address boundary. When false the core will wrap around internally, This violates the PCI specification ...
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... IDSEL signal. Register selection is defined by the contents of the address (bits 7 down to 2). A configuration write is shown in and a configuration read is shown in 23. CorePCI will also support burst transactions to configuration space if required. Memory / I/O Cycles Zero-Wait-State Burst Transactions Zero-wait-state bursting enables transfer of a DWORD (32-bit PCI) or two DWORDs (64-bit PCI) for every clock cycle ...
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... During cycle 7, TRDYn is asserted and valid data is driven onto the PCI bus. 4. The single DWORD transfer completes when TRDYn is de-asserted in cycle 8. Figure 6 • Configuration Read Cycle addr data0 Paddr Pdata0 1011 byte enables addr Paddr byte enables 1010 v4.0 CorePCI v5. data0 Pd0 23 ...
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... CorePCI v5.41 In the case of a PCI read, the backend must prefetch the memory data in order to ensure continuity on long bursts. If prefetching causes a problem, for example in a FIFO, the backend logic should shadow the last two data CLK FRAMEn AD PAR CBE IRDYn TRDYn ...
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... For this case, the PIPE_FULL_CNT is set to "000" (See Figure 8 • 32-Bit Burst Read with Zero Wait States addr data0 Paddr byte enables 0110 add0 add1 data0 data1 "Backend Latency Control" on page 31 v4.0 CorePCI v5. data1 data2 data3 Pd0 Pd1 Pd2 Pd3 add4 add5 add2 add3 data2 data3 data4 data5 for more information) ...
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... CorePCI v5.41 CLK FRAMEn REQ64n AD[63:32] AD[31:0] PAR PAR64 CBE IRDYn TRDYn STOPn DEVSELn ACK64n DP_START DP_START64 DP_DONE WR_BE_RDY WR_BE_NOW WR_BE_NOW64 MEM_ADDRESS MEM_DATA[63:32] MEM_DATA[31:0] Notes: 1. When FRAMEn and REQ64n is asserted and the command bus is '0111', then a 64-bit write to memory space is indicated. ...
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... Paddr zero byte enables 0110 add0 add2 data1 data3 data0 data2 "Backend Latency Control" on page 31 for RD_CYC and BARn_CYC timing. v4.0 CorePCI v5. data3 data5 data7 data2 data4 data6 Pd0 Pd2 Pd4 Pd6 Pd1 Pd3 Pd5 Pd7 ...
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... CorePCI v5.41 Paced Transactions Backend throttle transfers provide mechanism for supporting slow response devices. The backend transactions are paced using the RD_BE_RDY and WR_BE_RDY signals. These signals can be used to pace either single DWORD or burst transactions. CLK FRAMEn AD[31:0] PAR CBE[3:0] IRDYn ...
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... PCI bus. For writes, the backend must be prepared to accept up to two DWORDs of data prior to data transfer termination. For reads, the backend must be prepared to transmit one DWORD of data prior to data transfer termination. Paused transactions are shown in and Figure 14 on page v4.0 CorePCI v5. ...
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... CorePCI v5.41 CLK 1 2 FRAMEn AD[31:0] data2 data3 data4 Pd1 Pd2 PAR CBE[3:0] IRDYn TRDYn STOPn DEVSELn DP_START DP_DONE WR_BE_RDY WR_BE_NOW MEM_ADDRESS[23:2] add1 add2 MEM_DATA[31:0] data1 data2 data3 Notes the example, the flow of data is interrupted from the PCI Master de-assertion of IRDYn in cycle 3. The PCI Master inserts two wait states ...
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... Some backends require the address to be available at least one cycle prior to data being valid. This is true for most synchronous backends. In order to support this need, CorePCI provides the PIPE_FULL_CNT control bus to the backend. This bus can be used to define the relative delay between ...
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... CorePCI v5.41 1 CLK FRAMEn AD PAR CBE IRDYn TRDYn STOPn DEVSELn DP_START DP_DONE RD_BE_RDY RD_BE_NOW PIPE_FULL_CNT MEM_ADDRESS MEM_DATA Figure 15 • Backend Latency Read Transaction Target Abort The backend may cause a target abort abort, which is defined by the Target simultaneously asserting the STOPn signal and de-asserting the DEVSELn signal. ...
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... After several cycles, a PCI time-out will occur and the Target controller will initiate a Target disconnect without data cycle (Figure 18 on page addr Paddr 0110 byte enables v4.0 CorePCI v5.41 34 ...
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... CorePCI v5.41 CLK FRAMEn AD[31:0] PAR CBE[3:0] IRDYn TRDYn STOPn DEVSELn BUSY DP_START DP_DONE RD_BE_RDY RD_BE_NOW MEM_ADDRESS[23:2] MEM_DATA[31:0] Notes: 1. During a normal PCI transaction, the backend reaches a point where it is unable to deliver data and de-asserts RD_BE_RDY the backend cannot deliver new data within 8 cycles, then it should assert the BUSY signal. ...
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... PCI Master Transactions To perform Master transfers Target+DMA, and Target+Master functions, CorePCI controller has three configuration registers used to set addresses, transfer length, control, and check status of the transfer. A basic sequence of events for executing a DMA or Master transfer is as follows: 1. Write the location of the desired PCI address into the PCI Start Address register ...
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... WR_BE_NOW[3:0] Notes: 1. Once CorePCI is granted the PCI bus, the core asserts DP_START and begins the process of enabling the bus to drive FRAMEn. 2. The PCI address and command are valid at the same time that FRAMEn is driven low. 3. Once FRAMEn is driven, if the backend is prepared to supply data, then IRDYn is asserted on the following cycle. The core can store up to two DWORDs of data ...
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... RD_BE_NOW Notes: 1. Once CorePCI is granted the PCI bus, the core asserts DP_START and begins the process of enabling the bus to drive FRAMEn. 2. The PCI address and command are valid at the same time that FRAMEn is driven low. 3. Once FRAMEn is driven, if the backend is prepared to supply data, then IRDYn is asserted on the following cycle. The core can store up to two DWORDs of data ...
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... CorePCI v5.41 Backend Control of DMA Activity The core provides two signals, BUSY_MASTER and STALL_MASTER, that can be used to control the DMA transfers. BUSY_MASTER allows a DMA transfer to be stopped, and STALL_MASTER allows for slow backends to meet the FRAME-to-IRDY assertion requirement for PCI. If the backend asserts BUSY_MASTER when a DMA ...
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... Reads from the DMA are pipelined with two cycles of delay between valid address and valid data. To enable the output RD_CONTROLn must be driven low CLK 1 2 CS_CONTROLn WE_CONTROLn CONTROL_ADD[1:0] valid MEM_DATA[31:0] valid valid v4.0 CorePCI v5.41 data0 data1 data2 byte enables addr1 addr2 addr3 data1 data2 drivers, both CS_CONTROLn (Figure 26 ...
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... CorePCI v5.41 Ordering Information CorePCI v5.41 can be ordered through your local Actel sales representative. It should be ordered using the following numbering scheme; CorePCI-XX where XX corresponds to one of the variables in Table 23 • Ordering Codes XX Description EV Evaluation Version SN Netlist for single-use on Actel devices AN Netlist for unlimited use on Actel devices ...
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... This brief summarizes specific device and family information for unreleased products. Advanced This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. Unmarked (production) This datasheet version contains information that is considered to be final. v4.0 CorePCI v5.41 Page – 41 ...
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... Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel Corporation Actel Europe Ltd. 2061 Stierlin Court Dunlop House, Riverside Way Mountain View, CA Camberley, Surrey GU15 3YL 94043-4655 USA United Kingdom Phone 650.318.4200 Phone +44 (0) 1276 401 450 Fax 650 ...