CorePCI-AR Actel, CorePCI-AR Datasheet - Page 17

• Manufacturer Part Number: CorePCI-AR
• Description: Microcontroller Modules & Accessories CorePCI v5.41
• Manufacturer: Actel

Specifications of CorePCI-AR

• Product: Microcontroller Modules
• Data Bus Width: 32 bit, 64 bit
• Clock Speed: 66 MHz
• Flash: 256 Bytes
• Timers: 1

CorePCI Master Function
The Master function in CorePCI is designed to perform
the following:
Supported Master Commands
CorePCI Master controller is capable of performing
configuration, I/O, memory, and interrupt acknowledge
cycles. Data transfers can be up to 4kb. However,
configuration and I/O commands are typically limited to
a single DWORD.
The Master controller will attempt to complete the
transfer in a single burst unless the maximum burst
length bits are set in the control register. If the addressed
Target is unable to complete the transfer and performs a
Retry or Disconnect, the Master control will restart the
transfer and continue from the last known good transfer.
If a Target does not respond (no DEVSELn asserted) or
responds with Target Abort cycle, the Master controller
will abort the current transaction and report it as an
error in the control register. The supported CorePCI
Master commands are listed in
Table 17 • Supported CorePCI Master Commands
Table 19 • RAM Start Address
CBE[3:0]
0000
0010
Bit
1–0
23–2
31–24
Note: The description for bit values 31–24 and 23–2 will vary depending on the actual memory size defined in the customization options.
• Arbitrate for the PCI bus
• Initiate an access by asserting FRAMEn and
• Pass dataflow control to the Target controller
• End the transfer when the DMA count has been
providing the address and command
exhausted by de-asserting FRAMEn
See
"Customization Options" on page 19
Type
RO
RW
RO
Command Type
Interrupt Acknowledge Cycle
I/O Read
Table
Description
Set to '00'b. PCI transfers must be on a DWORD boundary.
RAM Start Address
This location will increment during the DMA transfer when the DMA_CNT_EN customization
constant is set to a '1'. Otherwise at the end of a transfer, this register value will hold the initial
starting address.
Set to all zeros.
17.
for more information. For this case, MADDR_WIDTH is set to 24.
v4.0
Table 17 • Supported CorePCI Master Commands
Master Registers
There are three registers used to control the function of
CorePCI Master. The first register is the 32-bit PCI address
register. The second register is the 32-bit RAM or
backend address register. These two registers provide the
source/destination addressing for all data transfers. A 32-
bit control register defines the type, length, and status of
a Master transfer. These registers are cleared on reset.
They are defined in detail in
this page, and
Table 18 • PCI Start Address
CBE[3:0]
0011
0110
0111
1010
1011
Bit
1–0
31–2
Type
RO
RW
Table 20 on page
Description
Set to '00'b. PCI transfers must be on a
DWORD boundary.
PCI Start Address
This location will increment during the DMA
transfer
customization constant is set to a '1'.
Otherwise at the end of a transfer, this
register value will hold the initial starting
address.
Command Type
I/O Write
Memory Read
Memory Write
Configuration Read
Configuration Write
when
Table 18
18.
the
and
CorePCI v5.41
DMA_CNT_EN
Table 19
on
17