CorePCI-AR Actel, CorePCI-AR Datasheet - Page 38

• Manufacturer Part Number: CorePCI-AR
• Description: Microcontroller Modules & Accessories CorePCI v5.41
• Manufacturer: Actel

Specifications of CorePCI-AR

• Product: Microcontroller Modules
• Data Bus Width: 32 bit, 64 bit
• Clock Speed: 66 MHz
• Flash: 256 Bytes
• Timers: 1

Backend Control of DMA Activity
The core provides two signals, BUSY_MASTER and
STALL_MASTER, that can be used to control the DMA
transfers. BUSY_MASTER allows a DMA transfer to be
stopped, and STALL_MASTER allows for slow backends to
meet the FRAME-to-IRDY assertion requirement for PCI.
If the backend asserts BUSY_MASTER when a DMA
transfer is taking place, the core will stop the DMA
Figure 23 • DMA Master with BUSY_MASTER Asserted
When a DMA backend read cycle is started the core will
start a backend read cycle by asserting DP_START and
two cycles later assert FRAME. Once FRAME is asserted
the PCI specification requires that the core assert IRDY
within 8 clock cycles. The core cannot assert IRDY until
the backend has asserted RD_BE_RDY. If the backend
3 8
CorePCI v5.41
MEM_ADDRESS[23:2]
MEM_DATA[31:0]
STALL_MASTER
BUSY_MASTER
RD_BE_NOW
RD_BE_RDY
DP_DONE
DEVSELn
FRAMEn
AD[31:0]
CBE[3:0]
RD_CYC
TRDYn
IRDYN
STOPn
addr
addr0
CMD
data0
data0
addr1
byte enables
data1
data1
v4.0
addr2 addr3
data2 data3 data4
transfer as soon as possible, as shown in Figure 22a. Due
to PCI protocol requirements the core may need to
transfer an additional two words after BUSY_MASTER
has been asserted.
transfer until BUSY_MASTER has been de-asserted. The
backend may assert BE_REQ at the same time, and when
BE_GNT is asserted may access the DMA control registers.
The backend can then clear the DMA request bit in the
control register to cancel the rest of the DMA transfer.
asserts RD_BE_RDY after 7 clock cycles, the core will
violate the PCI FRAME to IRDY assertion timing. In this
situation the backend should assert STALL_MASTER until
it can assert RD_BE_RDY, this will delay the core-asserting
FRAME until data is ready, causing the FRAME to IRDY
delay to be less than 8 clock cycles.
data2 data3
addr4
The core will not restart the DMA
addr4
CMD
data4