CorePCI-AR Actel, CorePCI-AR Datasheet - Page 13

• Manufacturer Part Number: CorePCI-AR
• Description: Microcontroller Modules & Accessories CorePCI v5.41
• Manufacturer: Actel

Specifications of CorePCI-AR

• Product: Microcontroller Modules
• Data Bus Width: 32 bit, 64 bit
• Clock Speed: 66 MHz
• Flash: 256 Bytes
• Timers: 1

Read-Only Configuration Registers
The read-only registers listed in
default values, but should be modified by the designer.
See the PCI specification for setting these values:
The header type register is also read-only, but should not
be modified (pre-set to a constant value of '00h'). The
Capability Pointer is included when the HOT_SWAP_EN
customization constant is set to '1'b. See
page 16
Table 8 • PCI Configuration Header
• Vendor ID
• Device ID
• Revision ID
• Class Code
• Subsystem ID
• Subsystem Vendor ID
Max_Lat
for more information.
31–24
BIST
Subsystem ID
Device ID
Status
Base Address #2 (Optional I/O for DMA Register Mapping)
Base Address #0 (Memory Location for Baseline Target)
Base Address #1 (Optional Memory or I/O)
Header Type
Class Code
Reserved
Min_Gnt
Interrupt Control/Status Register
Table 8 on page 13
23–16
Hot-Swap Register (optional)
Expansion ROM Base Address
CardBus CIS Pointer
Base Address #3
Base Address #4
Base Address #5
Reserved
Table 13 on
have
Latency Timer
Interrupt Pin
15–8
v4.0
Subsystem Vendor ID
Read/Write Configuration Registers
The following registers have at least one bit that is both
read and write capable. For a complete description, refer
to the appropriate table.
•
•
•
•
•
•
•
Command
Vendor ID
"Command Register (04h)" (Table 9 on page
" Status Register (06h)" (Table 10 on page
"Memory Base Address Register Bit Definition
(Locations 10h or 14h)" (Table 11 on page
"I/O
(Location 14h Only)" (Table 12 on page
"Interrupt Register (3Ch)" (Table 14 on page
"Interrupt Control/Status Register (48h)" (Table 15
on page
"Optional Hot-Swap Register (80h)" (Table 16 on
page
16)
Capabilities Pointer
Base
Cache Line Size
Interrupt Line
16)
Revision ID
7–0
Address
Register
Bit
Address
CorePCI v5.41
0Ch
1Ch
2Ch
3Ch
00h
04h
08h
10h
14h
18h
20h
24h
28h
30h
34h
38h
48h
80h
Definitions
16)
16)
14)
14)
16)
13