CorePCI-AR Actel, CorePCI-AR Datasheet - Page 36

• Manufacturer Part Number: CorePCI-AR
• Description: Microcontroller Modules & Accessories CorePCI v5.41
• Manufacturer: Actel

Specifications of CorePCI-AR

• Product: Microcontroller Modules
• Data Bus Width: 32 bit, 64 bit
• Clock Speed: 66 MHz
• Flash: 256 Bytes
• Timers: 1

Notes:
1. Once CorePCI is granted the PCI bus, the core asserts DP_START and begins the process of enabling the bus to drive FRAMEn.
2. The PCI address and command are valid at the same time that FRAMEn is driven low.
3. Once FRAMEn is driven, if the backend is prepared to supply data, then IRDYn is asserted on the following cycle. The core can store
4. The core then waits for the Target to complete the transfer by asserting TRDYn.
5. The transfer continues until either the transfer count is exhausted or the Target disconnects.
6. Cycle termination is initiated by driving FRAMEn high.
7. The number of clock cycles from DP_START to FRAMEn assertion can be increased by asserting STALL_MASTER.
Figure 21 • Zero-Wait-State Master DMA Read (Read from the PCI Bus)
PCI DMA Write
A DMA write begins by the core requesting control of
the bus. Once the bus is granted (GNTn asserted), the
core will initiate the transfer by asserting FRAMEn. A
DMA write reads information from RAM and writes
information onto the PCI bus. The backend begins
fetching data and when data is available, the datapath
pipe fills and data flows onto the PCI bus. At that point,
IRDYn is asserted and the burst transfer begins. The
transfer is terminated once the DMA transfer length is
3 6
CorePCI v5.41
up to two DWORDs of data. If the Target has not responded with a TRDYn when the second DWORD is read, then the core will cease
reading as indicated by the RD_BE_NOW signal de-asserting.
MEM_ADDRESS[23:2]
WR_BE_NOW[3:0]
MEM_DATA[31:0]
WR_BE_RDY
BARn_CYC
DP_START
DP_DONE
C_BE[3:0]
DEVSELn
AD[31:0]
FRAMEn
WR_CYC
TRDYn
STOPn
IRDYn
PAR
CLK
1
2
3
4
5
v4.0
6
reached.
burst write transfer.
To control the Master-only core, four backend signals have
been added. The new signals are CS_CONTROLn,
RD_CONTROLn, WR_CONTROLn and CONTROL_ADD(1:0).
Figure 25
signals are used to read and write the DMA control
registers, which in turn initiates PCI cycles.
7
CMD
addr
8
addr0
Paddr
Figure 22 on page 37
and
9
Figure 26 on page 39
10
data0
byte enables
11
data1
data0
Pd0
12
data2
addr1
data1
Pd1
13
shows the zero-wait-state
data3
addr2
data2
Pd2
14
addr3
data3
Pd3
show how these
15
addr4
16