MEDIA5200KIT1 Freescale Semiconductor, MEDIA5200KIT1 Datasheet - Page 20

MCU, MPU & DSP Development Tools MEDIA5200 SW DEVT SYSTEM

MEDIA5200KIT1

Manufacturer Part Number
MEDIA5200KIT1
Description
MCU, MPU & DSP Development Tools MEDIA5200 SW DEVT SYSTEM
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MEDIA5200KIT1

Processor To Be Evaluated
MPC5200B
Data Bus Width
32 bit
Interface Type
Ethernet, USB
Lead Free Status / Rohs Status
Not Compliant
20
Sample position A: data are sampled on the expected edge of MEM_CLK, the MDQS signal indicate the valid data
Sample position B: data are sampled on a later edge of MEM_CLK, SDRAM controller is waiting for the valid MDQS signal
NOTE: Control Signals signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN
MDQS (Data Strobe)
MBA (Bank Selects)
Sample Window
MDQS (Data Strobe)
Sample Window
MA (Address)
Control Signals
MDQ (Data)
Read Data
MDQ (Data)
Read Data
MEM_CLK
MEM_CLK
t
t
valid
valid
Figure 7. Timing Diagram—DDR SDRAM Memory Read Timing
t
valid
Active
Row
t
t
t
hold
hold
hold
NOP
MPC5200B Data Sheet, Rev. 4
Column
READ
t
data_sample_min
t
data_valid_min
NOP
t
data_valid_min
0.5
× t
MEM_CLK
NOP
t
data_sample_max
t
data_valid_max
NOP
t
t
data_sample_max
data_sample_min
t
data_valid_max
NOP
Freescale Semiconductor
NOP
Sample
position
Sample
position
A
B

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