AD5320BRM Analog Devices Inc, AD5320BRM Datasheet - Page 12

• Manufacturer Part Number: AD5320BRM
• Description: D/A Converter (D-A) IC
• Manufacturer: Analog Devices Inc

Specifications of AD5320BRM

• Resolution (bits): 12bit
• Digital Ic Case Style: MSOP
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +105°C
• Update Rate: 0.125MSPS
• Mounting Type: Surface Mount
• Peak Reflow Compatible (260 C): No
• Rohs Status: RoHS non-compliant
• Settling Time: 8µs
• Number Of Bits: 12
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power Dissipation (max): -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD5320
SERIAL INTERFACE
The AD5320 has a 3-wire serial interface ( SYNC , SCLK, and
DIN) that is compatible with SPI®, QSPI
MICROWIRE
Figure 2 for a timing diagram of a typical write sequence.
The write sequence begins by bringing the SYNC line low. Data
from the DIN line is clocked into the 16-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 30 MHz, making the AD5320 compatible with high speed
DSPs. On the 16th falling clock edge, the last data bit is clocked
in and the programmed function is executed (that is, a change
in DAC register contents and/or a change in the mode of
operation). At this stage, the SYNC line can be kept low or be
brought high. In either case, it must be brought high for a
minimum of 33 ns before the next write sequence so that a
falling edge of SYNC can initiate the next write sequence.
Because the SYNC buffer draws more current when V
than it does when V
between write sequences for even lower power operation of the
part. As previously mentioned, SYNC must be brought high
again just before the next write sequence.
INPUT SHIFT REGISTER
The input shift register is 16 bits wide (see Figure 25). The first two
bits are “don’t cares. ” The next two are control bits that control
which mode of operation the part is in (normal mode or any one of
three power-down modes). There is a more complete description of
the various modes in the Power-Down Modes section. The next
twelve bits are the data bits. These are transferred to the DAC
register on the 16th falling edge of SCLK.
TM
SCLK
SYNC
DIN
interface standards as well as most DSPs. See
IN
= 0.8 V, SYNC should be idled low
SYNC HIGH BEFORE 16TH FALLING EDGE
DB15
INVALID WRITE SEQUENCE:
DB15 (MSB)
X
X
TM
PD1
, and
PD0 D11 D10
DB0
0
0
1
1
0
1
0
1
IN
Figure 25. Input Register Contents
Figure 26. SYNC Interrupt Facility
NORMAL OPERATION
1kΩ TO GND
100kΩ TO GND
THREE–STATE
= 2.4 V
D9
Rev. C | Page 12 of 20
D8
D7
POWER-DOWN MODES
DATA BITS
D6
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for at
least 16 falling edges of SCLK and the DAC is updated on the
16th falling edge. However, if SYNC is brought high before the
16th falling edge, then this acts as an interrupt to the write
sequence. The shift register is reset and the write sequence is
seen as invalid. Neither an update of the DAC register contents
nor a change in the operating mode occurs (see Figure 26).
POWER-ON RESET
The AD5320 contains a power-on reset circuit that controls the
output voltage during power-up. The DAC register is filled with
zeros and the output voltage is 0 V. It remains there until a valid
write sequence is made to the DAC. This is useful in applica-
tions where it is important to know the state of the output of the
DAC while it is in the process of powering up.
VALID WRITE SEQUENCE, OUTPUT UPDATES
D5
DB15
ON THE 16TH FALLING EDGE
D4
D3
D2
DB0 (LSB)
D1
D0
DB0