AD5320BRM Analog Devices Inc, AD5320BRM Datasheet - Page 6

• Manufacturer Part Number: AD5320BRM
• Description: D/A Converter (D-A) IC
• Manufacturer: Analog Devices Inc

Specifications of AD5320BRM

• Resolution (bits): 12bit
• Digital Ic Case Style: MSOP
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +105°C
• Update Rate: 0.125MSPS
• Mounting Type: Surface Mount
• Peak Reflow Compatible (260 C): No
• Rohs Status: RoHS non-compliant
• Settling Time: 8µs
• Number Of Bits: 12
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power Dissipation (max): -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD5320
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
SOT-23
Pin No.
1
2
3
4
5
6
MSOP
Pin No.
4
8
1
7
6
5
2, 3
V
GND
V
OUT
DD
Figure 3. SOT-23 Pin Configuration
1
2
3
(Not to Scale)
Mnemonic
V
GND
V
DIN
SCLK
SYNC
NC
AD5320
TOP VIEW
OUT
DD
6
5
4
Description
Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and V
to GND.
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates up to 30 MHz.
Level Triggered Control Input (Active Low). This is the frame synchronization signal for the input data.
When SYNC goes low, it enables the input shift register and data is transferred in on the falling edges
of the following clocks. The DAC is updated following the 16th clock cycle unless SYNC is taken high
before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is
ignored by the DAC.
No Connect.
SYNC
SCLK
DIN
Rev. C | Page 6 of 20
V
V
OUT
NC
NC
DD
Figure 4. MSOP Pin Configuration
1
2
3
4
NC = NO CONNECT
(Not to Scale)
AD5320
TOP VIEW
8
7
6
5
DD
should be decoupled
GND
DIN
SCLK
SYNC