AD7674ACPZRL Analog Devices Inc, AD7674ACPZRL Datasheet - Page 10

• Manufacturer Part Number: AD7674ACPZRL
• Description: 18-Bit,800kSPSSARADC
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7674ACPZRL

• Number Of Bits: 18
• Sampling Rate (per Second): 800k
• Data Interface: Serial, Parallel
• Number Of Converters: 1
• Power Dissipation (max): 138mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7674CBZ - BOARD EVALUATION FOR AD7674
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7674
Pin No.
29
30
31
32
33
34
35
36
37
38
39
40–42,
45
43
46
48
49
(EPAD)
1
Table 7. Data Bus Interface Definitions
MODE
0
1
1
2
2
2
2
3
R[0:17] is the 18-bit ADC value stored in its output register.
AI = Analog Input; DI = Digital Input; DI/O = Bidirectional Digital; DO = Digital Output; P = Power.
MODE1
0
0
0
1
1
1
1
1
Mnemonic
BUSY
DGND
RD
CS
RESET
PD
CNVST
AGND
REF
REFGND
IN–
NC
IN+
REFBUFIN
PDBUF
Exposed Pad
MODE0
0
1
1
0
0
0
0
1
Type
DO
P
DI
DI
DI
DI
DI
P
AI
AI
AI
AI
AI
DI
D0/OB/2C
R[0]
OB/2C
OB/2C
OB/2C
OB/2C
OB/2C
OB/2C
OB/2C
1
Description
Busy Output. Transitions HIGH when a conversion is started. Remains HIGH until the conversion is
complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be used
as a data ready clock signal.
Must Be Tied to Digital Ground.
Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled.
Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is
also used to gate the external clock.
Reset Input. When set to a logic HIGH, reset the AD7674. Current conversion, if any, is aborted. If not
used, this pin could be tied to DGND.
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are
inhibited after the current one is completed.
Start Conversion. A falling edge on CNVST puts the internal sample/hold into the hold state and initiates
a conversion. In Impulse mode (IMPULSE HIGH, WARP LOW), if CNVST is held LOW when the acquisition
phase (t
Must Be Tied to Analog Ground.
Reference Input Voltage and Internal Reference Buffer Output. Apply an external reference on REF if the
internal reference buffer is not used. Should be decoupled effectively with or without the internal buffer.
Reference Input Analog Ground.
Differential Negative Analog Input.
No Connect.
Differential Positive Analog Input.
Reference Buffer Input Voltage. The internal reference buffer has a fixed gain. It outputs 4.096 V typically
when 2.5 V is applied on this pin.
Allows Choice of Buffering Reference. When LOW, buffer is selected. When HIGH, buffer is switched off.
The exposed pad is internally connected to AGND. This connection is not required to meet the electrical
performances however, for increased reliability of the solder joints, it is recommended that the pad be
soldered to the analog ground of the system.
8
) is complete, the internal sample/hold is put into hold and a conversion is immediately started.
D1/A0
R[1]
A0:0
A0:1
A0:0
A0:0
A0:1
A0:1
All Hi-Z
D2/A1
R[2]
R[2]
R[0]
A1:0
A1:1
A1:0
A1:1
Rev. A | Page 10 of 28
D[3]
R[3]
R[3]
R[1]
All Hi-Z
All Hi-Z
All Hi-Z
All Hi-Z
D[4:9]
R[4:9]
R[4:9]
D[10:11]
R[10:11]
R[10:11]
R[10:11]
R[2:3]
R[0:1]
Serial Interface
All Zeros
All Zeros
D[12:15]
R[12:15]
R[12:15]
R[12:15]
R[4:7]
All Zeros
D[16:17]
R[16:17]
R[16:17]
R[16:17]
R[8:9]
R[0:1]
Description
18-Bit Parallel
16-Bit High Word
16-Bit Low Word
8-Bit HIGH Byte
8-Bit MID Byte
8-Bit LOW Byte
8-Bit LOW Byte
Serial Interface