AD7674ACPZRL Analog Devices Inc, AD7674ACPZRL Datasheet - Page 22

• Manufacturer Part Number: AD7674ACPZRL
• Description: 18-Bit,800kSPSSARADC
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7674ACPZRL

• Number Of Bits: 18
• Sampling Rate (per Second): 800k
• Data Interface: Serial, Parallel
• Number Of Converters: 1
• Power Dissipation (max): 138mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7674CBZ - BOARD EVALUATION FOR AD7674
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7674
In Read after Conversion mode, it should be noted that unlike
in other modes, the BUSY signal returns low after the 18 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width.
SLAVE SERIAL INTERFACE
External Clock
The AD7674 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/ INT pin is
held high. In this mode, several methods can be used to read
the data. The external serial clock is gated by CS . When CS and
RD are both low, the data can be read after each conversion or
SDOUT
CS, RD
CNVST
SDOUT
CS, RD
CNVST
BUSY
SYNC
SCLK
BUSY
SYNC
SCLK
t
16
Figure 41. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)
t
3
EXT/INT = 0
t
t
t
t
14
15
15
16
t
14
t
X
t
17
29
t
t
22
18
Figure 40. Master Serial Data Timing for Reading (Read after Convert)
t
1
EXT/INT = 0
t
D17
3
t
1
20
X
t
t
19
22
t
21
t
20
D16
t
23
2
D17
1
t
t
19
18
Rev. A | Page 22 of 28
RDC/SDIN = 1
3
RDC/SDIN = 0
D16
t
t
21
2
23
t
28
3
To accommodate slow digital hosts, the serial clock can be
slowed down by using DIVSCLK.
during the following conversion. The external clock can be
either a continuous or a discontinuous clock. A discontinuous
clock can be either normally high or normally low when
inactive. Figure 42 and Figure 43 show the detailed timing
diagrams of these methods.
While the AD7674 is performing a bit decision, it is important
that voltage transients not occur on digital input/output pins or
16
D2
INVSCLK = INVSYNC = 0
INVSCLK = INVSYNC = 0
16
17
D1
D2
17
D1
18
t
24
D0
t
18
30
t
24
D0
03083-0-046
03083-0-040
t
t
t
25
27
26
t
t
t
26
25
27