AD7674ACPZRL Analog Devices Inc, AD7674ACPZRL Datasheet - Page 23

• Manufacturer Part Number: AD7674ACPZRL
• Description: 18-Bit,800kSPSSARADC
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7674ACPZRL

• Number Of Bits: 18
• Sampling Rate (per Second): 800k
• Data Interface: Serial, Parallel
• Number Of Converters: 1
• Power Dissipation (max): 138mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7674CBZ - BOARD EVALUATION FOR AD7674
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase because the AD7674 provides error correction circuitry
that can correct for an improper bit decision made during the
first half of the conversion phase. For this reason, it is
recommended that when an external clock is being provided, it
is a discontinuous clock that only toggles when BUSY is low or,
more importantly, that it does not transition during the latter
half of BUSY high.
External Discontinuous Clock Data Read after
Conversion
Though maximum throughput cannot be achieved using this
mode, it is the most recommended of the serial slave modes.
Figure 42 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
low, the result of this conversion can be read while both CS and
RD are low. Data is shifted out MSB first with 18 clock pulses,
and is valid on the rising and falling edge of the clock.
SDOUT
BUSY
SCLK
SDIN
CS
t
t
31
16
t
33
Figure 42. Slave Serial Data Timing for Reading (Read after Convert)
X
t
36
1
t
35
D17
X17
t
37
t
34
2
EXT/INT = 1
X16
D16
t
32
Rev. A | Page 23 of 28
3
X15
D15
INVSCLK = 0
Among the advantages of this method, the conversion
performance is not degraded because there are no voltage
transients on the digital interface during the conversion process.
Also, data can be read at speeds up to 40 MHz, accommodating
both slow digital host interface and the fastest serial reading.
Finally, in this mode only, the AD7674 provides a daisy-chain
feature using the RDC/SDIN input pin to cascade multiple
converters together. This feature is useful for reducing
component count and wiring connections when desired (for
instance, in isolated multiconverter applications).
An example of the concatenation of two devices is shown in
Figure 44. Simultaneous sampling is possible by using a
common CNVST signal. It should be noted that the RDC/SDIN
input is latched on the edge of SCLK opposite the one used to
shift out data on SDOUT. Thus, the MSB of the upstream
converter follows the LSB of the downstream converter on the
next SCLK cycle.
16
17
D1
X1
RD = 0
18
D0
X0
19
X17
Y17
20
03083-0-042
X16
Y16
AD7674