AD7721ARZ-REEL Analog Devices Inc, AD7721ARZ-REEL Datasheet

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AD7721ARZ-REEL

Manufacturer Part Number
AD7721ARZ-REEL
Description
16-BIT SIGMA DELTA A-D I.C.
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD7721ARZ-REEL

Number Of Bits
16
Sampling Rate (per Second)
468.75k
Data Interface
Serial, Parallel
Number Of Converters
1
Power Dissipation (max)
150mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-SOIC (0.300", 7.50mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
a
GENERAL DESCRIPTION
The AD7721 is a complete low power, 12-/16-bit, sigma-delta
ADC. The part operates from a +5 V supply and accepts a
differential input of 0 V to 2.5 V or 1.25 V. The analog input
is continuously sampled by an analog modulator at twice the
clock frequency eliminating the need for external sample-and-
hold circuitry. The modulator output is processed by two finite
impulse response (FIR) digital filters in series. The on-chip
filtering reduces the external antialias requirements to first order
in most cases. Settling time for a step input is 97.07 s while
the group delay for the filter is 48.53 s when the master clock
equals 15 MHz.
The AD7721 can be operated with input bandwidths up to
229.2 kHz. The corresponding output word rate is 468.75 kHz.
The part can be operated with lower clock frequencies also.
The sample rate, filter corner frequency and output word rate
will be reduced also, as these are proportional to the external
clock frequency. The maximum clock frequencies in parallel
mode and serial mode are 10 MHz and 15 MHz respectively.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FEATURES
16-Bit Sigma-Delta ADC
468.75 kHz Output Word Rate (OWR)
No Missing Codes
Low-Pass Digital Filter
High Speed Serial Interface
Linear Phase
229.2 kHz Input Bandwidth
Power Supplies: AV
Standby Mode (70 W)
Parallel Mode (12-Bit/312.5 kHz OWR)
DD
, DV
DD
: +5 V
5%
DVAL/SYNC
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
Use of a single bit DAC in the modulator guarantees excellent
linearity and dc accuracy. Endpoint accuracy is ensured by on-
chip calibration of offset and gain. This calibration procedure
minimizes the part’s zero-scale and full-scale errors.
The output data is accessed from the output register through a
serial or parallel port. This offers easy, high speed interfacing to
modern microcontrollers and digital signal processors. The
serial interface operates in internal clocking (master) mode, the
AD7721 providing the serial clock.
CMOS construction ensures low power dissipation while a
power-down mode reduces the power consumption to only
100 W.
STBY/DB0
CAL/DB1
DSUBST
UNI/DB2
DGND
DGND
VIN1
VIN2
468.75 kHz, Sigma-Delta ADC
WR
CS
RD
FUNCTIONAL BLOCK DIAGRAM
AD7721
DB3
AGND
World Wide Web Site: http://www.analog.com
DB4
MODULATOR
CONTROL LOGIC
AGND
12-BIT A/D CONVERTER
SYNC/
DB5
-
DB6
AV
DD
CMOS 16-Bit,
SCLK/
© Analog Devices, Inc., 1997
DB7
FILTER
FIR
DV
AD7721
DB8
DD
REFIN
DRDY
SDATA/DB11
DB9
CLK
RFS/DB10

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AD7721ARZ-REEL Summary of contents

Page 1

FEATURES 16-Bit Sigma-Delta ADC 468.75 kHz Output Word Rate (OWR) No Missing Codes Low-Pass Digital Filter High Speed Serial Interface Linear Phase 229.2 kHz Input Bandwidth Power Supplies Standby Mode (70 ...

Page 2

AD7721–SPECIFICATIONS Parameter SERIAL MODE ONLY STATIC PERFORMANCE Resolution Minimum Resolution for Which No Missing Codes Is Guaranteed Differential Nonlinearity Integral Nonlinearity DC CMRR 2 Offset Error Unipolar Mode Bipolar Mode 2, 3 Full-Scale Error Unipolar Mode Bipolar Mode Unipolar Offset ...

Page 3

SPECIFICATIONS REFIN = +2 Parameter PARALLEL MODE ONLY STATIC PERFORMANCE Resolution Minimum Resolution for Which No Missing Codes Is Guaranteed Differential Nonlinearity Integral Nonlinearity DC CMRR 2 Offset Error Unipolar Mode Bipolar Mode 2, 3 Full-Scale ...

Page 4

AD7721 TIMING CHARACTERISTICS Limit at T Parameter (A, S Versions) Serial Interface 3 f 100 CLK 15 t 0.45 t CLK LO CLK t 0.45 t CLK HI CLK CLK – CLK ...

Page 5

ABSOLUTE MAXIMUM RATINGS (T = +25 C unless otherwise stated DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V ...

Page 6

AD7721 Mnemonic Function AV Analog Positive Supply Voltage AGND Ground reference point for analog circuitry. DV Digital Supply Voltage DGND Ground reference point for digital circuitry. DGND must be connected via its own short ...

Page 7

Parallel Mode Only Mnemonic Function CS Chip Select Logic Input. RD Read Logic Input. This digital input is used in conjunction with CS to read data from the device. WR Write Logic Input. This digital input is used in conjunction ...

Page 8

AD7721 TERMINOLOGY Integral Nonlinearity This is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The end- points of the transfer function are zero scale (not to be con- fused with ...

Page 9

Input Circuits The purpose of antialiasing filters is to attenuate out of band signals that would otherwise be mixed down into the signal band. With traditional ADCs, high order filters using expensive high tolerance passive components are often required to ...

Page 10

AD7721 switching the positive input of the modulator to the reference voltage and the negative input to AGND. Again, when the modulator and digital filter settle, a gain correction factor is calculated from the average of 8 output results and ...

Page 11

CIRCUIT DESCRIPTION Sigma-Delta ADC The AD7721 ADC employs a sigma-delta conversion technique that converts the analog input into a digital pulse train. Due to the high oversampling rate, which spreads the quantiza- tion noise from /2, the ...

Page 12

AD7721 PARALLEL INTERFACE Read Operation The device defaults to parallel mode if CS, RD and WR are not tied to DGND together. Figure 11 shows a timing diagram for reading from the AD7721 in the parallel mode. When operating the ...

Page 13

MICROCOMPUTER/MICROPROCESSOR INTERFACING The AD7721 has a variety of interfacing options. It offers two operating modes—serial and parallel. Serial Interfacing In serial mode, the AD7721 can be directly interfaced to several DSPs. In all cases, the AD7721 operates as the master ...

Page 14

AD7721 Parallel Interface In parallel mode, the DRDY signal is still available. This signal can be used to generate an interrupt in the DSP as DRDY goes high for two clock cycles when a conversion is complete. Data is available ...

Page 15

A15–A0 EN ADDR IS DECODE CS IRQ STRB RD/W 1Y1 1G 2G 1A1 1Y2 1A2 1Y3 1A3 1Y4 1A4 HC244 2A1 2Y1 2Y2 2A2 2Y3 2A3 2Y4 2A4 D11– 1A1 1Y1 1Y2 1A2 TMS320C20/ 1Y3 1A3 1Y4 1A4 ...

Page 16

AD7721 0.250 (6.35) MAX 0.200 (5.05) 0.125 (3.18) 0.0118 (0.30) 0.0040 (0.10) 0.005 (0.13) MIN 0.225 (5.72) MAX 0.200 (5.08) 0.125 (3.18) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Plastic DIP (N-28) 1.565 (39.70) 1.380 (35.10 0.580 ...

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