AD7721ARZ-REEL Analog Devices Inc, AD7721ARZ-REEL Datasheet - Page 6

• Manufacturer Part Number: AD7721ARZ-REEL
• Description: 16-BIT SIGMA DELTA A-D I.C.
• Manufacturer: Analog Devices Inc

Specifications of AD7721ARZ-REEL

• Number Of Bits: 16
• Sampling Rate (per Second): 468.75k
• Data Interface: Serial, Parallel
• Number Of Converters: 1
• Power Dissipation (max): 150mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7721
Mnemonic
AV
AGND
DV
DGND
DSUBST
VIN1
VIN2
REFIN
CLK
Serial Mode Only
CS, RD, WR
DRDY
SDATA/DB11
RFS/DB10
DB9
DB8
SCLK/DB7
DB6
SYNC/DB5
DB4
DB3
UNI/DB2
CAL/DB1
STBY/DB0
DVAL/SYNC
DD
DD
Function
Analog Positive Supply Voltage, +5 V
Ground reference point for analog circuitry.
Digital Supply Voltage, +5 V
Ground reference point for digital circuitry. DGND must be connected via its own short path to AGND (Pin 24).
This is the substrate connection for digital circuits. It must be connected via its own short path to AGND
(Pin 24).
Analog Input. In unipolar operation, the analog input range on VIN1 is VIN2 to (VIN2 + V
operation, the analog input range on VIN1 is (VIN2
between 0 and AV
Reference Input. The AD7721 operates with an external reference, of value 2.5 V nominal. A suitable refer-
ence for operation with the AD7721 is the AD780. A 100 nF decoupling capacitor is required between
REFIN and AGND.
CMOS Logic Clock Input. The AD7721 operates with an external clock which is connected to the CLK pin.
The modulator samples the analog input on both phases of the clock, increasing the sampling rate to 20 MHz
(CLK = 10 MHz) or 30 MHz (CLK = 15 MHz).
To select the serial interface mode of operation, the AD7721 must be powered up with CS, RD and WR all
tied to DGND. After two clock cycles, the AD7721 switches into serial mode. These pins must remain low
during serial operation.
In the serial interface mode, a rising edge on DRDY indicates that new data is available to be read from the
interface. During a synchronization or calibration cycle, DRDY remains low until valid data is available.
Serial Data Output. Output serial data becomes active after RFS goes low. Sixteen bits of data are clocked
out starting with the MSB. Serial data is clocked out on the rising edge of SCLK and is valid on the subse-
quent falling edge of SCLK.
Receive Frame Synchronization. Active low logic input. This is a logic input with RFS provided by connect-
ing this input to DRDY. When RFS is high, SDATA is high impedance.
This is a test mode pin. This pin must be tied to DGND.
This is a test mode pin. This pin must be tied to DGND.
Serial Clock. Logic Output. The internal digital clock is provided as an output on this pin. Data is output
from the AD7721 on the rising edge of SCLK and is valid on the falling edge of SCLK.
This is a test mode pin. This pin must be tied to DGND.
Synchronization Logic Input. A rising edge on SYNC starts the synchronization cycle. SYNC must be
pulsed low for at least one clock cycle to initiate a synchronization cycle.
This is a test mode pin. This pin must be tied to DGND.
This is a test mode pin. This pin must be tied to DGND.
Analog Input Range Select, Logic Input. A logic low on this input selects unipolar mode. A logic high selects
bipolar mode.
Calibration Mode Logic Input. CAL must go high for at least one clock cycle to initiate a calibration cycle.
Standby Mode Logic Input. A logic high on this pin selects standby mode.
Data Valid Digital Output. In serial mode, this pin is a dedicated data valid pin.
DD
. The analog input is continuously sampled and processed by the analog modulator.
PIN FUNCTION DESCRIPTIONS
5%.
5%.
–6–
V
REFIN
/2). The absolute analog input range must lie
REFIN
); for bipolar
REV. A