AD9222ABCPZRL7-50 Analog Devices Inc, AD9222ABCPZRL7-50 Datasheet - Page 24

• Manufacturer Part Number: AD9222ABCPZRL7-50
• Description: Octal 12 Bit, 50 MSPS Serial LVDS ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9222ABCPZRL7-50

• Number Of Bits: 12
• Sampling Rate (per Second): 50M
• Data Interface: Serial, SPI™
• Number Of Converters: 8
• Power Dissipation (max): 760mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9222
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9222 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
This signal is typically ac-coupled to the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
and require no additional biasing.
Figure 63 shows a preferred method for clocking the AD9222. The
low jitter clock source is converted from a single-ended signal
to a differential signal using an RF transformer. The back-to-
back Schottky diodes across the secondary transformer limit
clock excursions into the AD9222 to approximately 0.8 V p-p
differential. This helps prevent the large voltage swings of the
clock from feeding through to other portions of the AD9222,
and it preserves the fast rise and fall times of the signal, which
are critical to low jitter performance.
Another option is to ac-couple a differential PECL signal to the
sample clock input pins as shown in Figure 64. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515
drivers offers excellent jitter performance.
1
1
50Ω RESISTORS ARE OPTIONAL.
50Ω RESISTORS ARE OPTIONAL.
CLK+
CLK+
CLK–
CLK+
CLK–
50Ω
50Ω
1
1
50Ω
Figure 63. Transformer-Coupled Differential Clock
0.1µF
Figure 65. Differential LVDS Sample Clock
Figure 64. Differential PECL Sample Clock
50Ω
0.1µF
0.1µF
0.1µF
0.1µF
50Ω
100Ω
1
1
ADT1-1WT, 1:1Z
MINI-CIRCUITS
CLK
CLK
CLK
CLK
LVDS DRIVER
PECL DRIVER
XFMR
0.1µF
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
240Ω
0.1µF
0.1µF
®
SCHOTTKY
HSM2812
DIODES:
240Ω
100Ω
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
family of clock
CLK+
CLK–
AD9222
CLK+
CLK–
CLK+
CLK–
ADC
AD9222
AD9222
ADC
ADC
Rev. D | Page 24 of 60
1
1
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be directly driven from a CMOS gate, and the
CLK− pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 66). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages of up to 3.3 V, making the
selection of the drive logic voltage very flexible.
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9222 contains a duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9222. When the DCS is on, noise and distortion perfor-
mance are nearly flat for a wide range of duty cycles. However,
some applications may require the DCS function to be off. If so,
keep in mind that the dynamic range performance can be affected
when operated in this mode. See the Memory Map section for
more details on using this feature.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately eight clock cycles
to allow the DLL to acquire and lock to the new rate.
50Ω RESISTOR IS OPTIONAL.
50Ω RESISTOR IS OPTIONAL.
CLK+
CLK+
50Ω
50Ω
Figure 66. Single-Ended 1.8 V CMOS Sample Clock
Figure 67. Single-Ended 3.3 V CMOS Sample Clock
0.1µF
0.1µF
1
1
0.1µF
0.1µF
CLK
CLK
CLK
CLK
CMOS DRIVER
CMOS DRIVER
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
0.1µF
OPTIONAL
OPTIONAL
100Ω
100Ω
39kΩ
0.1µF
0.1µF
0.1µF
CLK+
CLK–
CLK+
CLK–
AD9222
AD9222
ADC
ADC