AD9222ABCPZRL7-50 Analog Devices Inc, AD9222ABCPZRL7-50 Datasheet - Page 5

• Manufacturer Part Number: AD9222ABCPZRL7-50
• Description: Octal 12 Bit, 50 MSPS Serial LVDS ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9222ABCPZRL7-50

• Number Of Bits: 12
• Sampling Rate (per Second): 50M
• Data Interface: Serial, SPI™
• Number Of Converters: 8
• Power Dissipation (max): 760mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 3.
Parameter
CLOCK INPUTS (CLK+, CLK−)
LOGIC INPUTS (PDWN, SCLK/DTP)
LOGIC INPUT (CSB)
LOGIC INPUT (SDIO/ODM)
LOGIC OUTPUT (SDIO/ODM)
DIGITAL OUTPUTS (D + x, D − x),
DIGITAL OUTPUTS (D + x, D − x),
1
2
3
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
This is specified for LVDS and LVPECL only.
This is specified for 13 SDIO pins sharing the same connection.
Logic Compliance
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
Logic 1 Voltage (I
Logic 0 Voltage (I
(ANSI-644)
Logic Compliance
Differential Output Voltage (V
Output Offset Voltage (V
Output Coding (Default)
(Low Power, Reduced Signal
Option)
Logic Compliance
Differential Output Voltage (V
Output Offset Voltage (V
Output Coding (Default)
1
1
1
OH
OL
= 800 μA)
= 50 μA)
OS
OS
)
2
3
)
OD
OD
)
)
Temp
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
Full
Full
Full
Full
Min
250
1.2
0
1.2
0
1.2
0
247
1.125
150
1.10
CMOS/LVDS/LVPECL
Offset binary
Offset binary
AD9222-40
Typ
1.2
20
1.5
30
0.5
70
0.5
30
2
1.79
LVDS
LVDS
Max
3.6
0.3
3.6
0.3
DRVDD + 0.3
0.3
0.05
454
1.375
250
1.30
Rev. D | Page 5 of 60
Min
250
1.2
1.2
1.2
0
247
1.125
150
1.10
CMOS/LVDS/LVPECL
Offset binary
Offset binary
AD9222-50
Typ
1.2
20
1.5
30
0.5
70
0.5
30
2
1.79
LVDS
LVDS
Max
0.05
3.6
0.3
3.6
0.3
DRVDD + 0.3
0.3
454
1.375
250
1.30
Min
250
1.2
1.2
1.2
0
247
1.125
150
1.10
CMOS/LVDS/LVPECL
Offset binary
Offset binary
AD9222-65
Typ
1.2
20
1.5
30
0.5
70
0.5
30
2
1.79
LVDS
LVDS
Max
3.6
0.3
3.6
0.3
DRVDD + 0.3
0.3
0.05
454
1.375
250
1.30
AD9222
Unit
mV p-p
V
pF
V
V
pF
V
V
pF
V
V
pF
V
V
mV
V
mV
V
kΩ
kΩ
kΩ
kΩ