AD9467BCPZ-250 Analog Devices Inc, AD9467BCPZ-250 Datasheet - Page 25

• Manufacturer Part Number: AD9467BCPZ-250
• Description: 16 Bit 250 MSPS ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9467BCPZ-250

• Number Of Bits: 16
• Sampling Rate (per Second): 250M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1.45W
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 72-VFQFN, CSP Exposed Pad
• Number Of Elements: 1
• Resolution: 16Bit
• Architecture: Pipelined
• Sample Rate: 250MSPS
• Input Polarity: Bipolar
• Input Type: Voltage
• Rated Input Volt: ±1.25V
• Differential Input: Yes
• Power Supply Requirement: Single
• Single Supply Voltage (typ): 1.8/3.3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 1.45W
• Differential Linearity Error: ±1LSB(Typ)
• Integral Nonlinearity Error: ±3LSB(Typ)
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 72
• Package Type: LFCSP EP
• Input Signal Type: Differential
• Sampling Rate: 250MSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Supply Voltage Range - Digital: 1.7V To 1.9V
• Supply Current: 31mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

There are eight digital output test pattern options available that
can be initiated through the SPI. This is a useful feature when
validating receiver capture and timing. Refer to Table 10 for the
output bit sequencing options available. Some test patterns have
two serial sequential words and can be alternated in various
ways, depending on the test pattern chosen. Note that some
patterns may not adhere to the data format select option.
The PN sequence short pattern produces a pseudorandom bit
sequence that repeats itself every 2
tion of the PN sequence and how it is generated can be found
in Section 5.1 of the ITU-T 0.150 (05/96) standard. The only
difference is that the starting value must be a specific value
instead of all 1s (see Table 9 for the initial values).
The PN sequence long pattern produces a pseudorandom bit
sequence that repeats itself every 2
description of the PN sequence and how it is generated can be
found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The
only differences are that the starting value must be a specific
value instead of all 1s (see Table 9 for the initial values) and the
AD9467 inverts the bit stream with relation to the ITU standard.
Table 9. PN Sequence
Sequence
PN 9 Sequence, Short
PN 23 Sequence, Long
Table 10. Flexible Output Test Modes
Output Test Mode Bit Sequence
0000
0001
0010
0011
0100
0101
0110
0111
1
2
N/A = not applicable.
All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths to verify data capture to the receiver.
Initial
Value
0xFFFF
0x7FFF
9
23
− 1 or 511 bits. A descrip-
– 1 or 8,388,607 bits. A
First Three Output
Samples (MSB First)
0x87BE, 0xAE64, 0x929D
0x7E00, 0x807C, 0x801F
Pattern Name
Off (default)
Midscale short
+Full-scale short
−Full-scale short
Checkerboard
PN sequence long
PN sequence short
One-/zero-word toggle
2
2
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Digital Output Word 1
N/A
1000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
1010 1010 1010 1010
N/A
N/A
1111 1111 1111 1111
1
1
1
Consult the Memory Map section for information on how to
change these additional digital output timing features through
the SPI.
Overrange (OR) Output Pins
The OR+ and OR− output pins indicate when an applied analog
input is above or below the input full scale of the converter.
If the analog input is in an overrange condition, the OR bit goes
high, coinciding with output data hitting above or below full-
scale. The delay between the time the part actually overranges
and the OR bit going high is the pipeline latency of the part.
SPI Pins: SCLK, SDIO, CSB
For normal SPI operation, these pins should be tied to AGND
through a 100 kΩ resistor on each pin. These pins are both
1.8 V and 3.3 V tolerant. However, the SDIO output logic level
is dependent on the bias of the SPIVDD pin. For 3.3 V output
logic, tie SPIVDD to 3.3 V (AVDD2). For 1.8 V output logic, tie
SPIVDD to 1.8 V (AVDD1).
The CSB pin should be tied to AVDD1 for applications that do
not require SPI mode operation. By tying CSB high, all SCLK
and SDIO information is ignored.
Digital Output Word 2
N/A
Same
Same
Same
0101 0101 0101 0101
N/A
N/A
0000 0000 0000 0000
1
1
1
Subject to Data
Format Select
N/A
Yes
Yes
Yes
No
Yes
Yes
No
1
AD9467