AD9467BCPZ-250 Analog Devices Inc, AD9467BCPZ-250 Datasheet - Page 27

• Manufacturer Part Number: AD9467BCPZ-250
• Description: 16 Bit 250 MSPS ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9467BCPZ-250

• Number Of Bits: 16
• Sampling Rate (per Second): 250M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1.45W
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 72-VFQFN, CSP Exposed Pad
• Number Of Elements: 1
• Resolution: 16Bit
• Architecture: Pipelined
• Sample Rate: 250MSPS
• Input Polarity: Bipolar
• Input Type: Voltage
• Rated Input Volt: ±1.25V
• Differential Input: Yes
• Power Supply Requirement: Single
• Single Supply Voltage (typ): 1.8/3.3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 1.45W
• Differential Linearity Error: ±1LSB(Typ)
• Integral Nonlinearity Error: ±3LSB(Typ)
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 72
• Package Type: LFCSP EP
• Input Signal Type: Differential
• Sampling Rate: 250MSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Supply Voltage Range - Digital: 1.7V To 1.9V
• Supply Current: 31mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SCLK
Table 12. Serial Timing Definitions
Parameter
t
t
t
t
t
t
t
t
t
SDIO
DS
DH
CLK
S
H
HIGH
LOW
EN_SDIO
DIS_SDIO
CSB
DON’T CARE
DON’T CARE
Timing (Minimum, ns)
5
2
40
5
2
16
16
10
10
t
S
R/W
t
DS
W1
W0
t
DH
A12
t
HIGH
Description
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the clock
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 68)
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising
edge (not shown in Figure 68)
A11
A10
t
LOW
Figure 68. Serial Timing Details
A9
Rev. B | Page 27 of 32
t
CLK
A8
A7
D5
D4
D3
D2
D1
D0
t
H
DON’T CARE
AD9467
DON’T CARE