AD9467BCPZ-250 Analog Devices Inc, AD9467BCPZ-250 Datasheet - Page 28

• Manufacturer Part Number: AD9467BCPZ-250
• Description: 16 Bit 250 MSPS ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9467BCPZ-250

• Number Of Bits: 16
• Sampling Rate (per Second): 250M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1.45W
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 72-VFQFN, CSP Exposed Pad
• Number Of Elements: 1
• Resolution: 16Bit
• Architecture: Pipelined
• Sample Rate: 250MSPS
• Input Polarity: Bipolar
• Input Type: Voltage
• Rated Input Volt: ±1.25V
• Differential Input: Yes
• Power Supply Requirement: Single
• Single Supply Voltage (typ): 1.8/3.3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 1.45W
• Differential Linearity Error: ±1LSB(Typ)
• Integral Nonlinearity Error: ±3LSB(Typ)
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 72
• Package Type: LFCSP EP
• Input Signal Type: Differential
• Sampling Rate: 250MSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Supply Voltage Range - Digital: 1.7V To 1.9V
• Supply Current: 31mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9467
MEMORY MAP
READING THE MEMORY MAP TABLE
Each row in the memory map register table (see Table 13) has
eight address locations. The memory map is divided into three
sections: the chip configuration register map (Address 0x00
to Address 0x02), the device index and transfer register map
(Address 0xFF), and the ADC functions register map
(Address 0x08 to Address 0x107).
The leftmost column of the memory map indicates the register
address number, and the default value is shown in the second right-
most column. The (MSB) Bit 7 column is the start of the default
hexadecimal value given. For example, Address 0x2C, the analog
input register, has a default value of 0x00, meaning Bit 7 = 0,
Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and
Bit 0 = 0, or 0000 0000 in binary. This setting is the default for an
ac-coupled analog input condition. By writing a 1 to Bit 2 of this
address, the internal input common-mode buffer is disabled
allowing a dc-coupled input for which the input common mode
voltage can be set externally. For more information on this and
other functions, consult the
Interfacing to High Speed ADCs via SPI.
Table 13. Memory Map Register
Addr.
(Hex)
Chip Configuration Register
00
01
02
Device Index and Transfer Register
FF
Parameter Name
chip_grade
device_update
chip_port_config
chip_id
(MSB)
Bit 7
X
X
X
AN-877
1
Application Note,
Bit 6
LSB first
1 = on
0 = off
(default)
X
(identify device variants of chip ID)
001 = 200 MSPS
010 = 250 MSPS
Child ID Bits[6:4]
Bit 5
Soft
reset
1 = on
0 = off
(default)
X
(AD9467 = 0x50, default)
Bit 4
1
X
8-Bit Chip ID Bits[7:0]
Rev. B | Page 28 of 32
Bit 3
1
X
X
RESERVED LOCATIONS
Undefined memory locations should not be written to except
when writing the default values suggested in this data sheet.
Addresses that have values marked as 0 should be considered
reserved and have a 0 written into their registers during power-up.
DEFAULT VALUES
When the AD9467 comes out of a reset, critical registers are
preloaded with default values. These values are indicated in
Table 13, where an X refers to an undefined feature.
LOGIC LEVELS
An explanation of various registers follows: “Bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit. ” Similarly, “clear a bit” is synonymous with “bit is set to
Logic 0” or “writing Logic 0 for the bit. ”
Bit 2
X
X
X
Bit 1
X
X
X
(LSB)
Bit 0
X
X
SW
transfer
1 = on
0 = off
(default)
Default
Value
(Hex)
0x18
Read
only
Read
only
0x00
Default is
unique chip ID,
different for
each device.
This is a read-
only register.
Default Notes/
Comments
The nibbles
should be
mirrored so
that LSB- or
MSB-first mode
is set correctly
regardless of
shift mode.
Child ID used to
differentiate
graded devices.
Synchronously
transfers data
from the
master shift
register to the
slave.