AD9520-0/PCBZ Analog Devices Inc, AD9520-0/PCBZ Datasheet - Page 20

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AD9520-0/PCBZ

Manufacturer Part Number
AD9520-0/PCBZ
Description
12/24 Channel Clock Gen 2,0GH
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9520-0/PCBZ

Design Resources
Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
Main Purpose
Timing, Clock Generator
Utilized Ic / Part
AD9520-0
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD9520-0
Pin No.
48
50
51
52
53
55
56
58
62
63
64
EPAD
Input/
Output
O
O
O
O
O
O
O
O
O
I
I
Pin
Type
LVPECL or
CMOS
LVPECL or
CMOS
LVPECL or
CMOS
LVPECL or
CMOS
LVPECL or
CMOS
LVPECL or
CMOS
LVPECL or
CMOS
Current set
resistor
Current set
resistor
Reference
input
Reference
input
GND
Mnemonic
OUT3 (OUT3A)
OUT2 (OUT2B)
OUT2 (OUT2A)
OUT1 (OUT1B)
OUT1 (OUT1A)
OUT0 (OUT0B)
OUT0 (OUT0A)
RSET
CPRSET
REFIN (REF2)
REFIN (REF1)
GND
Along with REFIN, this is the differential input for the PLL reference.
Description
Clock Output. This pin can be configured as one side of a differential LVPECL
output or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVPECL
output or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVPECL
output or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVPECL
output or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVPECL
output or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVPECL
output or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVPECL
output or as a single-ended CMOS output.
Clock Distribution Current Set Resistor. Connect a 4.12 kΩ resistor from this pin to
GND.
Charge Pump Current Set Resistor. Connect a 5.1 kΩ resistor from this pin to
GND.
This resistor can be omitted if the PLL is not used.
Alternatively, this pin is a single-ended input for REF2.
Along with REFIN, this is the differential input for the PLL reference.
Alternatively, this pin is a single-ended input for REF1.
Exposed die pad must be connected to GND.
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