AD9520-0/PCBZ Analog Devices Inc, AD9520-0/PCBZ Datasheet - Page 45

• Manufacturer Part Number: AD9520-0/PCBZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc

Specifications of AD9520-0/PCBZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Main Purpose: Timing, Clock Generator
• Utilized Ic / Part: AD9520-0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Either the internal VCO or the CLK can be selected as the
source for the direct-to-output signal routing. To connect the
LVPECL outputs directly to the internal VCO or CLK, the user
must select the VCO divider as the source to the distribution
section, even if no channel uses it.
Table 32. Routing VCO Divider Input Directly to the Outputs
Register Setting
0x1E1[1:0] = 00b
0x1E1[1:0] = 10b
0x192[1] = 1b
0x195[1] = 1b
0x198[1] = 1b
0x19B[1] = 1b
Clock Frequency Division
The total frequency division is a combination of the VCO
divider (when used) and the channel divider. When the VCO
divider is used, the total division from the VCO or CLK to the
output is the product of the VCO divider (1, 2, 3, 4, 5, and 6)
and the division of the channel divider. Table 33 indicates how the
frequency division for a channel is set.
Table 33. Frequency Division
CLK or VCO
Selected
CLK or VCO
input
CLK or VCO
input
CLK or VCO
input
CLK or VCO
input
CLK
(internal
VCO off)
CLK
(internal
VCO off)
1
The channel dividers feeding the output drivers contain one 2-
to-32 frequency divider. This divider provides for division-by-1
to division-by-32. Division-by-1 is accomplished by bypassing
the divider. The dividers also provide for a programmable duty
cycle, with optional duty-cycle correction when the divide ratio
is odd. A phase offset or delay in increments of the input clock
cycle is selectable. The channel dividers operate with a signal at
their inputs up to 1600 MHz. The features and settings of the
dividers are selected by programming the appropriate setup
and control registers (see Table 49 through Table 60).
The bypass VCO divider (0x1E1[0] = 1) is not the same as VCO divider = 1.
VCO
Divider
Setting
1 to 6
1 to 6
2 to 6
1
VCO
divider
bypassed
VCO
divider
bypassed
1
Selection
CLK is the source; VCO divider selected
VCO is the source; VCO divider selected
Direct-to-output OUT0, OUT1, OUT2
Direct-to-output OUT3, OUT4, OUT5
Direct-to-output OUT6, OUT7, OUT8
Direct-to-output OUT9, OUT10, OUT11
Channel
Divider
Setting
Don’t
care
2 to 32
Bypass
Bypass
Bypass
2 to 32
Direct-to-
Output
Setting
Enable
Disable
Disable
Disable
Don’t
care
Don’t
care
Resulting
Frequency
Division
1
(1 to 6) ×
(2 to 32)
(2 to 6) × (1)
Output static
(illegal state)
1
2 to 32
Rev. 0 | Page 45 of 84
VCO Divider
The VCO divider provides frequency division between the
internal VCO or the external CLK input and the clock
distribution channel dividers. The VCO divider can be set
to divide by 1, 2, 3, 4, 5, or 6 (see Table 56, 0x1E0[2:0]).
However, when the VCO divider is set to 1, none of the channel
output dividers can be bypassed.
The VCO divider can also be set to static, which is useful for
applications where the only desired output frequency is the
VCO frequency. Making the VCO divider static increases the
wide band spurious-free dynamic range (SFDR). If the VCO
divider is static during VCO calibration, there is no output
signal. Therefore, it is recommended that the user calibrate the
VCO with the VCO divider set to a nonstatic value during VCO
calibration, and then set the VCO divider to static after VCO
calibration is complete.
The recommended alternative to achieving the same SFDR
performance is to set the VCO divider to 1 and enable VCO
direct mode. This allows the user to program the EEPROM
with the desired values and does not require further action after
the VCO calibration is complete.
Channel Dividers
A channel divider drives each group of three LVPECL outputs.
There are four channel dividers (0, 1, 2, and 3) driving 12 LVPECL
outputs (OUT0 to OUT11). Table 34 gives the register locations
used for setting the division and other functions of these dividers.
The division is set by the values of M and N. The divider can be
bypassed (equivalent to divide-by-1, divider circuit is powered
down) by setting the bypass bit. The duty-cycle correction can
be enabled or disabled according to the setting of the disable div
DCC bits.
Table 34. Setting D
Divider
0
1
2
3
Channel Frequency Division (0, 1, 2, and 3)
For each channel (where the channel number is x 0, 1, 2, or 3),
the frequency division, D
(four bits each, representing decimal 0 to decimal 15), where
The high and low cycles are cycles of the clock signal currently
routed to the input of the channel dividers (VCO divider out or
CLK).
When a divider is bypassed, D
Otherwise, D
each channel divider to divide by any integer from 1 to 32.
Number of Low Cycles = M + 1
Number of High Cycles = N + 1
Low Cycles
M
0x190[7:4]
0x193[7:4]
0x196[7:4]
0x199[7:4]
X
= (N + 1) + (M + 1) = N + M + 2. This allows
X
for the Output Dividers
X
High Cycles
N
0x190[3:0]
0x193[3:0]
0x196[3:0]
0x199[3:0]
, is set by the values of M and N
X
= 1.
Bypass
0x191[7]
0x194[7]
0x197[7]
0x19A[7]
AD9520-0
Disable
Div DCC
0x192[0]
0x195[0]
0x198[0]
0x19B[0]