AD9600ABCPZ-125 Analog Devices Inc, AD9600ABCPZ-125 Datasheet - Page 43

• Manufacturer Part Number: AD9600ABCPZ-125
• Description: 10Bit 125Msps Dual 1.8V PB Free ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9600ABCPZ-125

• Number Of Bits: 10
• Sampling Rate (per Second): 125M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 800mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Addr
(Hex)
0x10A
0x10B
0x10C
0x10D
0x10E
0x10F
0x110
0x111
0x112
0x113
0x114
0x115
0x116
0x117
Register
Name
Increase Gain
Dwell Time
Register 0
(Local)
Increase Gain
Dwell Time
Register 1
(Local)
Signal Monitor
DC Correction
Control
(Global)
Signal Monitor
DC Value
Channel A
Register 0
(Global)
Signal Monitor
DC Value
Channel A
Register 1
(Global)
Signal Monitor
DC Value
Channel B
Register 0
(Global)
Signal Monitor
DC Value
Channel B
Register 1
(Global)
Signal Monitor
SPORT Control
(Global)
Signal Monitor
Control
(Global)
Signal Monitor
Period
Register 0
(Global)
Signal Monitor
Period
Register 1
(Global)
Signal Monitor
Period
Register 2
(Global)
Signal Monitor
Result
Channel A
Register 0
(Global)
Signal Monitor
Result
Channel A
Register 1
(Global)
Bit 7
(MSB)
Open
Open
Open
Open
Complex
power
calculation
mode
enable
Bit 6
DC
correction
freeze
Open
Open
RMS/MS
magnitude
output
enable
Open
Bit 5
Peak
detector
output
enable
Open
Signal Monitor Result Channel A [15:8]
Signal Monitor Result Channel A [7:0]
Increase Gain Dwell Time [15:8]
Increase Gain Dwell Time [7:0]
DC Correction Bandwidth [3:0]
Signal Monitor Period [23:16]
Signal Monitor Period [15:8]
Signal Monitor Period [7:0]
DC Value Channel A [7:0]
DC Value Channel B [7:0]
Bit 4
Threshold
crossing
output
enable
Open
Rev. B | Page 43 of 72
DC Value Channel A [13:8]
DC Value Channel B [13:8]
Bit 3
SPORT SMI
SCLK divide
00 = undefined
01 = divide by 2
10 = divide by 4
11 = divide by 8
Signal
monitor
rms/ms
select
0 = rms
1 = ms
Bit 2
Signal monitor mode
00 = rms/ms magnitude
01 = peak power
10 = threshold crossing
11 = threshold crossing
Bit 1
DC
correction
for signal
path
enable
SPORT
SMI SCLK
sleep
Bit 0
(LSB)
DC
correction
for signal
monitor
enable
Signal
monitor
SPORT
output
enable
Signal
monitor
enable
0x00
0x00
0x40
0x00
0x00
Default
Value
(Hex)
0x00
0x04
0x00
AD9600
Default
Notes/
Comments
In ADC clock
cycles.
In ADC clock
cycles.
Read only.
Read only.
Read only.
Read only
In ADC clock
cycles.
In ADC clock
cycles.
In ADC clock
cycles.
Read only.
Read only.