AD9640-125EBZ Analog Devices Inc, AD9640-125EBZ Datasheet - Page 28

• Manufacturer Part Number: AD9640-125EBZ
• Description: 14Bit 125MspsDual 1.8V PB Free ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9640-125EBZ

• Design Resources: Interfacing ADL5534 to AD9640 High Speed ADC (CN0049)
• Number Of Adc's: 2
• Number Of Bits: 14
• Sampling Rate (per Second): 125M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 910mW @ 125MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9640
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9640-150EBZ - BOARD EVALUATION AD9640 150MSPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9640
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
6 kΩ load (see Figure 15). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1 V.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9640 sample clock inputs
CLK+, and CLK− should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
(see Figure 55) and require no external bias.
Clock Input Options
The AD9640 has a very flexible clock input structure. Clock input
can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of
the type of signal being used, the jitter of the clock source is of the
most concern, as described in the Jitter Considerations section.
Figure 56 and Figure 57 show two preferred methods for clocking
the AD9640 (at clock rates to 625 MHz). A low jitter clock source
is converted from a single-ended signal to a differential signal
using either an RF balun or an RF transformer. The RF balun
configuration is recommended for clock frequencies between
125 MHz and 625 MHz, and the RF transformer is recommended
for clock frequencies from 10 MHz to 200MHz. The back-to-back
Schottky diodes across the transformer/balun secondary limit
clock excursions into the AD9640 to approximately 0.8 V p-p
differential.
–0.5
–1.0
–1.5
–2.0
–2.5
2.5
2.0
1.5
1.0
0
CLK+
–40
Figure 55. Equivalent Clock Input Circuit
–20
2pF
Figure 54. Typical VREF Drift
0
TEMPERATURE (°C)
AVDD
1.2V
20
40
60
2pF
CLK–
80
Rev. B | Page 28 of 52
This helps prevent the large voltage swings of the clock from
feeding through to other portions of the AD9640, while preserving
the fast rise and fall times of the signal that are critical to a low
jitter performance.
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 58. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515/AD9516
jitter performance.
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 59. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516 clock
drivers offer excellent jitter performance.
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended CMOS signal. In such applica-
tions, CLK+ should be directly driven from a CMOS gate, and
the CLK− pin should be bypassed to ground with a 0.1 μF
capacitor in parallel with a 39 kΩ resistor (see Figure 60).
CLOCK
CLOCK
CLOCK
CLOCK
INPUT
INPUT
CLOCK
INPUT
INPUT
INPUT
CLOCK
INPUT
Figure 56. Transformer Coupled Differential Clock (Up to 200 MHz)
50kΩ
50kΩ
Figure 57. Balun Coupled Differential Clock (Up to 625 MHz)
Figure 59. Differential LVDS Sample Clock (Up to 625 MHz)
Figure 58. Differential PECL Sample Clock (Up to 625 MHz)
50Ω
0.1µF
50Ω
1nF
0.1µF
0.1µF
50kΩ
0.1µF
0.1µF
50kΩ
1nF
100Ω
ADT1–1WT, 1:1Z
MINI-CIRCUITS
AD951x
PECL DRIVER
AD951x
LVDS DRIVER
0.1µF
XFMR
240Ω
0.1µF
0.1µF
0.1µF
0.1µF
clock drivers offer excellent
SCHOTTKY
SCHOTTKY
HSMS2822
HSMS2822
DIODES:
DIODES:
240Ω
100Ω
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
CLK+
CLK–
AD9640
CLK+
CLK–
AD9640
ADC
CLK+
CLK–
CLK+
CLK–
AD9640
AD9640
ADC
ADC
ADC