AD9640-125EBZ Analog Devices Inc, AD9640-125EBZ Datasheet - Page 37

• Manufacturer Part Number: AD9640-125EBZ
• Description: 14Bit 125MspsDual 1.8V PB Free ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9640-125EBZ

• Design Resources: Interfacing ADL5534 to AD9640 High Speed ADC (CN0049)
• Number Of Adc's: 2
• Number Of Bits: 14
• Sampling Rate (per Second): 125M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 910mW @ 125MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9640
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9640-150EBZ - BOARD EVALUATION AD9640 150MSPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DC Correction Bandwidth
The dc correction circuit is a high-pass filter with a programmable
bandwidth (ranging between 0.15 Hz and 1.2 kHz at 125 MSPS).
The bandwidth is controlled by writing Bits[5:2] of the signal
monitor dc correction control register, located at Address 0x10C.
The following equation can be used to compute the bandwidth
value for the dc correction circuit:
where:
k is the 4 bit value programmed in Register 0x10C, Bits[5:2]
(values between 0 and 13 are valid for k; programming 14 or
15 provides the same result as programming 13).
f
DC Correction Readback
The current dc correction value can be read back in Register 0x10D
and Register 0x10E for Channel A and in Register 0x10F and
Register 0x110 for Channel B. The dc correction value is a 14-bit
value that can span the entire input range of the ADC.
DC Correction Freeze
Setting Bit 6 of Register 0x10C freezes the dc correction at its
current state and continues to use the last updated value as the
dc correction value. Clearing this bit restarts dc correction and
adds the currently calculated value to the data.
DC Correction Enable Bits
Setting Bit 0 of Register 0x10C enables dc correction for use in
the signal monitor calculations. The calculated dc correction
value can be added to the output data signal path by setting Bit 1
of Register 0x10C.
CLK
SMI SCLK
SMI SDFS
SMI SDO
SMI SCLK
SMI SDFS
is the ADC sample rate in hertz (Hz).
SMI SDO
DC
_
Corr
_
BW
MSB
=
20 CYCLES
MSB
2
RMS/MS CH A
−
k
−
14
20 CYCLES
RMS/MS CH A
×
Figure 71. Signal Monitor SPORT Output Timing (RMS/MS, Peak, and Threshold Enabled)
2
f
CLK
LSB
×
Figure 72. Signal Monitor SPORT Output Timing (RMS/MS and Threshold Enabled)
π
16 CYCLES
LSB
PK CH A
16 CYCLES
16 CYCLES
THR CH A
THR CH A
Rev. B | Page 37 of 52
MSB
MSB
20 CYCLES
20 CYCLES
RMS/MS CH B LSB
RMS/MS CH B
SIGNAL MONITOR SPORT OUTPUT
The SPORT is a serial interface with three output pins:
SMI SCLK (SPORT clock), SMI SDFS (SPORT frame sync), and
SMI SDO (SPORT data output). The SPORT is the master and
drives all three SPORT output pins on the chip.
SMI SCLK
The data output and frame sync are driven on the positive edge of
the SMI SCLK. The SMI SCLK has three possible baud rates: 1/2,
1/4, or 1/8 the ADC clock rate, based on the SPORT controls. The
SMI SCLK can also be gated off when not sending any data, based
on the SPORT SMI SCLK sleep bit. Using this bit to disable the SMI
SCLK when it is not needed can reduce any coupling errors back
into the signal path, if these prove to be a problem in the system.
Doing so, however, has the disadvantage of spreading the frequency
content of the clock. If desired, the SMI SCLK can be left running
to ease frequency planning.
SMI SDFS
The SMI SDFS is the serial data frame sync, and it defines the
start of a frame. One SPORT frame includes data from both
datapaths. The data from Datapath A is sent just after the frame
sync, followed by data from Datapath B.
SMI SDO
The SMI SDO is the serial data output of the block. The data
is sent MSB first on the next positive edge after the SMI SDFS.
Each data output block includes one or more rms/ms magnitude,
peak level, and threshold crossing values from each datapath in
the stated order. If enabled, the data is sent, rms first, followed by
peak and threshold, as shown in Figure 71.
GATED, BASED ON CONTROL
LSB
GATED, BASED ON CONTROL
16 CYCLES
PK CH B
16 CYCLES
THR CH B
16 CYCLES
THR CH B
RMS/MS CH A
RMS/MS CH A
AD9640