AD9786-EBZ Analog Devices Inc, AD9786-EBZ Datasheet - Page 27

• Manufacturer Part Number: AD9786-EBZ
• Description: 16 BIT DAC W/2/4/8x INTERPOLATION FILTER
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9786-EBZ

• Number Of Dac's: 1
• Number Of Bits: 16
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 500M
• Data Interface: Parallel
• Dac Type: Current
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9786
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CLOCK/DATA TIMING
Table 26. Data Port Synchronization
DCLKEXT
0x02, Bit 3
1
1
0
0
0
0
Two-Port Data Input Mode (DATACLK Master)
With the interpolation set to 1×, the DATACLK output is a
delayed and inverted version of DACCLK at the same frequency.
Note that DACCLK refers to the differential clock inputs applied
at Pin 5 and Pin 6. As Figure 44 and Figure 45 show, there is a
constant delay between the edges of DACCLK and DATACLK.
The DCLKPOL bit (Register 0x02, Bit 4) allows the data to be
latched into the AD9786 upon either the rising or falling edge
of DACCLK. With DCLKPOL = 0, the data is latched in upon
the falling edge of DACCLK, as shown in Figure 44. With
DCLKPOL = 1, as shown in Figure 45, data is latched in upon
the rising edge of DACCLK. The setup and hold times are
always with respect to the latching edge of DACCLK.
t
D
= 6ns TYP
Figure 44. Data Timing, 1× Interpolation, DCLKPOL = 0
Figure 45. Data Timing, 1× Interpolation, DCLKPOL = 1
t
D
= 5.5ns TYP
t
S
= –0.5ns MIN
t
MODSYNC
0x05, Bit 3
0
1
0
0
1
1
S
= –0.5ns MIN
t
H
= 2.9ns MIN
t
H
= 2.9ns MIN
t
12
DATACLK
DATACLK
DCLKCRC
0x02, Bit 2
X
X
0
1
0
1
DACCLK
DACCLK
DATA
DATA
OUT
OUT
IN
IN
Rev. B | Page 27 of 56
With the interpolation set to 2×, the DACCLK input runs at
twice the speed of the DATACLK. Data is latched into the digital
inputs of the AD9786 upon every other rising edge of DACCLK,
as shown in Figure 47 and Figure 48. With DCLKPOL = 0, as
shown in Figure 47, the latching edge of DACCLK is the rising
edge that occurs just before the falling edge of DATACLK. With
DCLKPOL = 1, as in Figure 48, the latching edge of DACCLK is
the rising edge of DACCLK that occurs just before the rising edge
of DATACLK. The setup and hold time values are identical to
those in Figure 44 and Figure 45.
Note that there is a slight difference in the delay from the rising
edge of DACCLK to the falling edge of DATACLK, and the
delay from the rising edge of DACCLK to the rising edge of
DATACLK. As Figure 46 shows, the DATACLK duty cycle is
slightly less than 50%. This is true in all modes.
With the interpolation set to 4× or 8×, the DACCLK input
runs at 4× or 8× the speed of the DATACLK output. The data
is latched in upon a rising edge of DACCLK, similar to the
2× interpolation mode.
However, the latching edge is every fourth edge in 4× inter-
polation mode and every eighth edge in the 8× interpolation
mode. Similar to operation in the 2× interpolation mode, with
DCLKPOL = 0, the latching edge of DACCLK is the rising edge
that occurs just before the falling edge of DATACLK. With
DCLKPOL = 1, the latching edge of DACCLK is the rising
edge that occurs just before the rising edge of DATACLK.
The setup and hold time values are identical to those in 1×
and 2× interpolation.
Mode
DATACLK Master
Modulator Master
External Sync Mode
DATACLK Slave
Low Setup/Hold
Modulator Slave
Function
Channel data rate clock output
Modulator synchronization
DATACLK output
DATACLK inactive, DACCLK
synchronous with external data
DATACLK input, data rate clock,
data recovery on
DATACLK input, input data
synchronous with DATACLK
Input modulator synchronizer
DATACLK input
AD9786