AD9786-EBZ Analog Devices Inc, AD9786-EBZ Datasheet - Page 28

• Manufacturer Part Number: AD9786-EBZ
• Description: 16 BIT DAC W/2/4/8x INTERPOLATION FILTER
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9786-EBZ

• Number Of Dac's: 1
• Number Of Bits: 16
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 500M
• Data Interface: Parallel
• Dac Type: Current
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9786
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9786
DATACLK Slave Mode (Data Recovery On)
DATACLK (Pin 31) can be used as an input to synchronize
multiple AD9786s. A clock generated by an AD9786 operating
in master mode, or a clock from an external source, can be used
to drive DATACLK.
In this mode, two clocks are required to be applied to the
AD9786. A clock running at the DAC sample rate, referred to as
DACCLK, must be applied to the differential inputs (Pin 5 and
Pin 6) of the AD9786. As described previously, a clock at the
input sample rate must also be applied to Pin 31 (DATACLK).
An internal DLL synchronizes the two applied clocks. The
timing relationships between the input data, DATACLK, and
DACCLK are given in Figure 49 and Figure 50.
t
D
= 6ns TYP
Figure 47. Data Timing, 2× Interpolation, DCLKPOL = 0
Figure 48. Data Timing, 2× Interpolation, DCLKPOL = 1
t
D
= 5ns TYP
t
Figure 46. DATACLK Duty Cycle
S
t
S
= –0.5ns MIN
= –0.5ns MIN
t
H
= 2.9ns MIN
t
H
= 2.9ns MIN
DACCLK
DATACLK
DATA
DACCLK
DATACLK
IN
DATA
OUT
IN
OUT
Rev. B | Page 28 of 56
Note that DCLKPOL (Register 0x02, Bit 4) can be used to select
the edge of DACCLK upon which the input data is latched.
There is a defined setup-and-hold window with respect to input
data and the latching edge of DACCLK. There is also a required
timing relationship between DATACLK and DACCLK. This is
referred to in Figure 49 and Figure 50 as t
hold for transition). For example, with DCLKPOL set to Logic 0,
the input data latches upon the first rising edge of DACCLK
that occurs more than 1.5 ns before the falling edge of DATACLK.
DACCLK should not be given a rising edge in the window of
500 ps to 1.5 ns before the latching edge (falling edge when
DCLKPOL = 0, rising edge when DCLKPOL = 1) of DATACLK.
Failure to account for this timing relationship could result in
corrupt data.
There are three status bits available for a read that allow the user
to verify DLL lock. These are Bit 0, Bit 1, and Bit 2 (DCRCSTAT) in
Register 0x12.
t
HT
t
ST
= 1.5ns MIN
= –1.0ns MIN
Figure 49. Slave Mode Timing, 2× Interpolation, DCLKPOL = 0
Figure 50. Slave Mode Timing, 2× Interpolation, DCLKPOL = 1
t
ST
t
= –500ps MIN
S
= 0.0ns MIN
t
S
= 0.0ns MIN
t
HT
= 2.0ns MIN
t
H
= 3.2ns MIN
t
H
= 3.2ns MIN
ST
and t
HT
DATACLK
DACCLK
DATACLK
(setup and
DACCLK
DATA
DATA
IN
IN
IN
IN