AD9883ABSTZ-140 Analog Devices Inc, AD9883ABSTZ-140 Datasheet
AD9883ABSTZ-140
Specifications of AD9883ABSTZ-140
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AD9883ABSTZ-140 Summary of contents
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FEATURES Industrial Temperature Range Operation 140 MSPS Maximum Conversion Rate 300 MHz Analog Bandwidth 0 1.0 V Analog Input Range 500 ps p-p PLL Clock Jitter at 110 MSPS 3.3 V Power Supply Full Sync Processing Sync ...
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AD9883A–SPECIFICATIONS Analog Interface ( Parameter Temp Level RESOLUTION DC ACCURACY Differential Nonlinearity 25°C Full Integral Nonlinearity 25°C Full No Missing Codes Full ANALOG INPUT Input Voltage Range Minimum Full Maximum Full Gain Tempco 25°C Input ...
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Parameter Temp Level DIGITAL OUTPUTS Output Voltage, High (V ) Full OH Output Voltage, Low (V ) Full OL Duty Cycle DATACK Full Output Coding POWER SUPPLY V Supply Voltage Full D V Supply Voltage Full DD P Supply Voltage ...
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AD9883A Analog Interface ( Parameter Temp Level RESOLUTION DC ACCURACY Differential Nonlinearity 25°C Full Integral Nonlinearity 25°C Full ANALOG INPUT Input Voltage Range Minimum Full Maximum Full Gain Tempco 25°C Input Bias Current 25°C Full ...
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Parameter Temp Level POWER SUPPLY V Supply Voltage Full D V Supply Voltage Full DD P Supply Voltage Full VD I Supply Current (V ) 25° Supply Current (V ) 25° Supply Current ...
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AD9883A ABSOLUTE MAXIMUM RATINGS ...
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GND GREEN <7> GREEN <6> GREEN <5> GREEN <4> GREEN <3> GREEN <2> GREEN <1> GREEN <0> GND V DD BLUE <7> BLUE <6> BLUE <5> BLUE <4> BLUE <3> BLUE <2> BLUE <1> BLUE <0> GND Pin Type Mnemonic ...
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AD9883A Pin Name Function OUTPUTS HSOUT Horizontal Sync Output A reconstructed and phase-aligned version of the Hsync input. Both the polarity and duration of this output can be pro- grammed via serial bus registers. By maintaining alignment with DATACK and ...
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Pin Name Function CLAMP External Clamp Input This logic input may be used to define the time during which the input signal is clamped to ground. It should be exer- cised when the reference dc level is known to be ...
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AD9883A At that point the signal should be resistively terminated (75 Ω to the signal ground return) and capacitively coupled to the AD9883A inputs through 47 nF capacitors. These capacitors form part of the dc restoration circuit ideal ...
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OFFSET = 7FH 1.0 0 00H GAIN Figure 2. Gain and Offset Control Gain and Offset Control The AD9883A can accommodate input signals with inputs ranging from 0 1.0 V full scale. The full-scale range is ...
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AD9883A The PLL characteristics are determined by the loop filter design, by the PLL Charge Pump Current, and by the VCO range setting. The loop filter design is illustrated in Figure 6. Recommended settings of VCO range and charge pump ...
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Table V. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats Refresh Standard Resolution Rate 640 × 480 VGA 800 × 600 SVGA ...
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AD9883A RGB HSYNC PxCK HS 5-PIPE DELAY ADCCK DATACK D OUTA HSOUT RGB HSYNC PxCK HS 5-PIPE DELAY ADCCK DATACK G OUTA R OUTA HSOUT ...
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Serial Register Map The AD9883A is initialized and controlled by a set of registers, which determine the operating modes. An external controller is Write and Hex Read or Default Address Read Only Bits Value 00H RO 7:0 01H* R/W ...
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AD9883A Write and Hex Read or Default Address Read Only Bits Value 0FH R/W 7:1 0******* *1****** **0***** ***0**** ****1*** *****1** ******1* 10H R/W 7:3 10111*** *****0** ******0* *******0 11H R/W 7:0 00100000 12H R/W 7:0 00000000 13H R/W 7:0 ...
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Write and Hex Read or Default Address Read Only Bits Value 16H R/W 7:0 17H RO 7:0 18H RO 7:0 *The AD9883A only updates the PLL divide ratio when the LSBs are written to (register 02H). 2-WIRE SERIAL CONTROL REGISTER ...
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AD9883A 04 7–3 Clock Phase Adjust A 5-bit value that adjusts the sampling phase in 32 steps across one pixel time. Each step represents an 11.25° shift in sampling phase. The power-up default value is 16. CLAMP TIMING 05 7–0 ...
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Hsync Output Polarity This bit determines the polarity of the Hsync output and the SOG output. Table XI shows the effect of this option. SYNC indicates the logic state of the sync pulse. Table XI. Hsync Output Polarity ...
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AD9883A 0F 4 Coast Input Polarity Override This register is used to override the internal circuitry that determines the polarity of the Coast signal going into the PLL. Table XX. Coast Input Polarity Override Settings Override Bit Result 0 Determined ...
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Post-Coast This register allows the coast signal to be applied follow- ing the Vsync signal. This is necessary in cases where post-equalization pulses are present. The step size for this control is one Hsync period. The default is ...
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AD9883A Table XXXIV. Detected Coast Input Polarity Status Polarity Status Result 0 Coast Polarity Negative 1 Coast Polarity Positive This indicates that Bit 1 of Register 5 is the 4:2:2 Output mode select bit 4:2:2 Output Mode Select ...
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Data is read from the control registers of the AD9883A in a similar manner. Reading requires two data transfer operations: The base address must be written with the R/W Bit of the slave address byte low to set up a ...
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AD9883A Table XXXVIII. Control of the Sync Block Muxes via the Serial Register Serial Bus Control Mux No. Control Bit Bit State Result 1 and 2 0EH: Bit 3 0 Pass Hsync 1 Pass Sync-on-Green 3 0FH: Bit 5 0 ...
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It is also recommended to use a single ground plane for the entire board. Experience has repeatedly shown that the noise perfor- mance is the same or better with a single ground plane. Using multiple ground planes can be detrimental ...
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AD9883A 10 1. 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90 CCW OUTLINE DIMENSIONS 80-Lead Low Profile Quad Flat Package [LQFP] (ST-80) Dimensions shown in millimeters 0.75 1.60 0.60 MAX 0. SEATING PIN 1 ...
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Revision History Location 8/03—Data Sheet changed from REV REV. B. Added B Grade models . . . . . . . . . . . . . . . . . . . . . . . . ...
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