ADC10D020CIVS National Semiconductor, ADC10D020CIVS Datasheet

ADC10D020CIVS

Manufacturer Part Number

ADC10D020CIVS

Description

IC,A/D CONVERTER,DUAL,10-BIT,CMOS,TQFP,48PIN

Manufacturer

National Semiconductor

Datasheets

1.ADC10D020CIVS.pdf (31 pages)

2.ADC10D020CIVS.pdf (32 pages)

Specifications of ADC10D020CIVS

Rohs Compliant

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ADC10D020

Dual 10-Bit, 20 MSPS, 150 mW A/D Converter

General Description

The ADC10D020 is a dual low power, high performance

CMOS analog-to-digital converter that digitizes signals to 10

bits resolution at sampling rates up to 30 MSPS while con-

suming a typical 150 mW from a single 3.0V supply. No

missing codes is guaranteed over the full operating tempera-

ture range. The unique two stage architecture achieves 9.5

Effective Bits over the entire Nyquist band at 20 MHz sample

rate. An output formatting choice of offset binary or 2’s

complement coding and a choice of two gain settings eases

the interface to many systems. Also allowing great flexibility

of use is a selectable 10-bit multiplexed or 20-bit parallel

output mode. An offset correction feature minimizes the off-

set error.

To ease interfacing to most low voltage systems, the digital

output power pins of the ADC10D020 can be tied to a

separate supply voltage of 1.5V to 3.6V, making the outputs

compatible with other low voltage systems. When not con-

verting, power consumption can be reduced by pulling the

PD (Power Down) pin high, placing the converter into a low

power state where it typically consumes less than 1 mW and

from which recovery is less than 1 ms. Bringing the STBY

(Standby) pin high places the converter into a standby mode

where power consumption is about 27 mW and from which

recovery is 800 ns.

The ADC10D020’s speed, resolution and single supply op-

eration makes it well suited for a variety of applications,

including high speed portable applications.

Operating over the industrial (−40˚ ≤ T

ture range, the ADC10D020 is available in a 48-pin TQFP. An

evaluation board is available to ease the design effort.

Connection Diagram

DS200255

≤ +85˚C) tempera-

TOP VIEW

Features

n Internal sample-and-hold

n Internal reference capability

n Dual gain settings

n Offset correction

n Selectable offset binary or 2’s complement output

n Multiplexed or parallel output bus

n Single +2.7V to 3.6V operation

n Power down and standby modes

Key Specifications

n Resolution

n Conversion Rate

n ENOB

n DNL

n Conversion Latency Parallel Outputs

n PSRR

n Power Consumption — Normal Operation

Applications

n Digital Video

n CCD Imaging

n Portable Instrumentation

n Communications

n Medical Imaging

n Ultrasound

— Multiplexed Outputs, I Data Bus

— Multiplexed Outputs, Q Data Bus

— Power Down Mode

— Fast Recovery Standby Mode

20025501

2.5 Clock Cycles

3 Clock Cycles

February 2005

0.35 LSB (typ)

150 mW (typ)

www.national.com

9.5 Bits (typ)

27 mW (typ)

1 mW (typ)

20 MSPS

10 Bits

90 dB

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