ADSP-21062KS-160 Analog Devices Inc, ADSP-21062KS-160 Datasheet - Page 38

• Manufacturer Part Number: ADSP-21062KS-160
• Description: Digital Signal Processor IC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21062KS-160

• Supply Voltage Max: 5.25V
• Dsp Type: Fixed / Floating Point
• Mounting Type: Surface Mount
• Package / Case: 240-MQFP
• Memory Organization - Ram: 2M
• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 256kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: 0°C ~ 85°C
• Package: 240MQFP
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 40 MHz
• Ram Size: 256 KB
• Device Million Instructions Per Second: 40 MIPS

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Link Ports —1 × CLK Speed Operation
Table 23. Link Ports—Receive
1
2
3
Table 24. Link Ports—Transmit
1
2
3
4
5
6
Parameter
Timing Requirements
t
t
t
t
t
Switching Characteristics
t
t
t
t
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
For ADSP-21062, specification is 3 ns min.
LACK goes low with t
For ADSP-21060C, specification is 18 + DT/2 ns min, 29 + DT/2 ns max.
For ADSP-21060L/ADSP-21060LC, specification is 20 ns min.
For ADSP-21060L, specification is 16.5 ns max; for ADSP-21060LC, specification is 16.75 ns max.
For ADSP-21062, specification is 2.5 ns max.
For ADSP-21062, specification is (t
For ADSP-21062, specification is (t
For ADSP-21062, specification is (t
SLDCL
HLDCL
LCLKIW
LCLKRWL
LCLKRWH
DLAHC
DLALC
ENDLK
TDLK
SLACH
HLACH
DLCLK
DLDCH
HLDCH
LCLKTWL
LCLKTWH
DLACLK
ENDLK
TDLK
specification is (t
specification is (t
ADSP-21060LC specification is (t
Data Setup Before LCLK Low
Data Hold After LCLK Low
LCLK Period (1u Operation)
LCLK Width Low
LCLK Width High
LACK High Delay After CLKIN High
LACK Low Delay After LCLK High
LACK Enable From CLKIN
LACK Disable From CLKIN
CK
CK
/2) – 1 ns min, (t
/2) – 2.25 ns min, (t
DLALC
LACK Setup Before LCLK High
LACK Hold After LCLK High
Data Delay After CLKIN (1u
Operation)
Data Delay After LCLK High
Data Hold After LCLK High
LCLK Width Low
LCLK Width High
LCLK Low Delay After LACK High
LACK Enable From CLKIN
LACK Disable From CLKIN
relative to rise of LCLK after first nibble, but does not go low if the receiver’s link buffer is not about to fill.
CK
CK
CK
CK
/2) + 8 ns min, (3 × t
2
CK
/2) – 1 ns min, (t
/2) – 1.25 ns min, (t
/2) + 8.75 ns min, (3 × t
/2) + 2.25 ns max.
CK
/2) + 1 ns max.
4
5
1
CK
/2) + 1.25 ns max; for ADSP-21062L, specification is (t
3
CK
CK
2, 3
/2) + 1 ns max; for ADSP-21062L, specification is (t
1
/2) + 18.5 ns max.
CK
Rev. F | Page 38 of 64 | March 2008
6
/2) + 17 ns max; for ADSP-21062L, specification is (t
Min
18
–7
–3
(t
(t
(t
5 + DT/2
CK
CK
CK
/2) – 2
/2) – 2
/2) + 8.5
Min
3.5
3
t
6
5
18 + DT/2
–3
5 + DT/2
CK
5 V
Max
15.5
3
(t
(t
(3 u t
20 + DT/2
CK
CK
5 V
/2) + 2
/2) + 2
Max
28.5 + DT/2
+13
20 + DT/2
CK
/2) + 17
CK
CK
/2) – 1 ns min, (t
/2) – 1.5 ns min, (t
Min
18
–7
–3
(t
(t
(t
5 + DT/2
CK
CK
CK
CK
/2) + 8 ns min, (3 × t
Min
3
3
t
6
5
18 + DT/2
–3
5 + DT/2
/2) – 1
/2) – 1.25
/2) + 8
CK
CK
CK
/2) + 1.5 ns max; for ADSP-21060LC
3.3 V
/2) + 1 ns max; for ADSP-21060C
3.3 V
Max
15.5
2.5
(t
(t
(3 u t
20 + DT/2
CK
CK
CK
Max
28.5 + DT/2
+13
20 + DT/2
/2) + 17 ns max; for
/2) + 1.25
/2) + 1
CK
/2) + 17.5 ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns