ADSP-21160NCB-100 Analog Devices Inc, ADSP-21160NCB-100 Datasheet - Page 2

• Manufacturer Part Number: ADSP-21160NCB-100
• Description: IC,DSP,32-BIT,CMOS,BGA,400PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21160NCB-100

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 100MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.90V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Package: 400BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 100 MHz
• Ram Size: 512 KB
• Device Million Instructions Per Second: 100 MIPS

ADSP-21160M/ADSP-21160N
Single-instruction, multiple-data (SIMD)
Parallelism in buses and computational units allows
Memory attributes
DMA controller supports
Multiprocessing support provides
Serial ports provide
64-bit-wide synchronous external port provides
architecture provides
Two computational processing elements
Concurrent execution—each processing element executes
Code compatibility—at assembly level, uses the same
Single-cycle execution (with or without SIMD) of a multiply
Transfers between memory and core at up to four
Accelerated FFT butterfly computation through a multiply
4M bits on-chip dual-ported SRAM for independent access
4G word address range for off-chip memory
Memory interface supports programmable wait state gen-
14 zero-overhead DMA channels for transfers between
64-bit background DMA transfers at core clock speed, in
Host processor interface to 16- and 32-bit microprocessors
Glueless connection for scalable DSP multiprocessing
Distributed on-chip bus arbitration for parallel bus con-
6 link ports for point-to-point connectivity and array
Two synchronous serial ports with companding hardware
Independent transmit and receive functions
TDM support for T1 and E1 interfaces
Glueless connection to asynchronous and SBSRAM exter-
the same instruction, but operates on different data
instruction set as the ADSP-2106x SHARC DSPs
operation, an ALU operation, a dual memory read or
write, and an instruction fetch
32-bit floating- or fixed-point words per cycle
with add and subtract
by core processor, host, and DMA
eration and page-mode for off-chip memory
ADSP-21160x internal memory and external memory,
external peripherals, host processor, serial ports, or link
ports
parallel with full-speed processor execution
architecture
nect of up to 6 ADSP-21160x processors plus host
multiprocessing
nal memories
Rev. B | Page 2 of 60 | February 2010