ADSP-21368BBPZ-2A Analog Devices Inc, ADSP-21368BBPZ-2A Datasheet - Page 38

• Manufacturer Part Number: ADSP-21368BBPZ-2A
• Description: IC,DSP,32-BIT,CMOS,BGA,256PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21368BBPZ-2A

• Interface: DAI, DPI
• Clock Rate: 333MHz
• Non-volatile Memory: ROM (768 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA Exposed Pad, 256-eBGA, 256-HBGA
• Device Core Size: 32/40Bit
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 333MHz
• Mips: 333
• Device Input Clock Speed: 333MHz
• Ram Size: 256KB
• Program Memory Size: 768KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: SBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21367/ADSP-21368/ADSP-21369
Input Data Port
The timing requirements for the IDP are given in
signals SCLK, frame sync (FS), and SDATA are routed to the
DAI_P20–1 pins using the SRU. Therefore, the timing specifica-
tions provided below are valid at the DAI_P20–1 pins.
Table 32. IDP
1
Parameter
Timing Requirements
t
t
t
t
t
t
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
SISFS
SIHFS
SISD
SIHD
IDPCLKW
IDPCLK
1
1
1
1
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
SDATA Setup Before SCLK Rising Edge
SDATA Hold After SCLK Rising Edge
Clock Width
Clock Period
DAI_P20–1
DAI_P20–1
DAI_P20–1
(SDATA)
(SCLK)
(FS)
Table
Rev. E | Page 38 of 60 | July 2009
Figure 25. IDP Master Timing
t
IPDCLKW
32. IDP
t
SISFS
SAMPLE EDGE
t
SISD
t
t
SIHFS
SIHD
t
IPDCLK
Min
4
2.5
2.5
2.5
(t
t
PCLK
PCLK
× 4
× 4) ÷ 2 – 1
Max
Unit
ns
ns
ns
ns
ns
ns