ADSP-BF504BCPZ-3F Analog Devices Inc, ADSP-BF504BCPZ-3F Datasheet - Page 47

• Manufacturer Part Number: ADSP-BF504BCPZ-3F
• Description: Blackfin W/Processor & Executable Flash
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF504BCPZ-3F

• Interface: CAN, EBI/EMI, I²C, IrDA, PPI, SPI, SPORT, UART/USART
• Clock Rate: 300MHz
• Non-volatile Memory: FLASH (16MB)
• On-chip Ram: 68kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.29V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADC Controller Module (ACM) Timing
Table 41
Note that the ACM clock (ACLK) frequency in MHz is set by
the following equation (in which ACMCKDIV ranges from
0 to 255).
Table 41. ACM Timing
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
SDR
HDR
DO
DACLK
DCS
DCSACLK
SPORT DRxPRI/DRxSEC Setup Before ACLK
SPORT DRxPRI/DRxSEC Hold After ACLK
ACM Controls (ACM_A[2:0], ACM_RANGE, ACM_SGLDIFF) Delay
After Falling Edge of CLKOUT
ACLK Delay After Falling Edge of CLKOUT
The Delay Between the Active Edge of CS and the First Edge of
ACLK
and
CS Active Edge Delay After Falling Edge of CLKOUT
Figure 30
f
ACLK
CONTROLS
CLKOUT
DRxSEC
DRxPRI/
ACLK
ACM
=
describe ACM operations.
--------------------------------------------------------
t
DCS
2
t
DCSACLK
ACMCKDIV
f
SCLK
+
2
Rev. 0 | Page 47 of 80 | December 2010
t
DO
Figure 30. ACM Timing
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
Min
8.0
0
t
ACLK
t
– 5
SDR
V
DDEXT
t
HDR
= 1.8 V
Max
8.4
4.5
5.6
t
DACLK
t
ACLK
Min
7.0
0
t
ACLK
=
– 5
V
------------- -
f
ACLK
DDEXT
1
= 2.5 V/3.3 V
Max
8.4
4.5
5.3
Units
ns
ns
ns
ns
ns
ns