ADSP-BF504BCPZ-3F Analog Devices Inc, ADSP-BF504BCPZ-3F Datasheet - Page 7

• Manufacturer Part Number: ADSP-BF504BCPZ-3F
• Description: Blackfin W/Processor & Executable Flash
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF504BCPZ-3F

• Interface: CAN, EBI/EMI, I²C, IrDA, PPI, SPI, SPORT, UART/USART
• Clock Rate: 300MHz
• Non-volatile Memory: FLASH (16MB)
• On-chip Ram: 68kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.29V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 3. System Interrupt Controller (SIC)
Peripheral Interrupt Source
PLL Wakeup Interrupt
DMA Error (generic)
PPI Status
SPORT0 Status
SPORT1 Status
UART0 Status
UART1 Status
SPI0 Status
SPI1 Status
CAN Status
RSI Mask 0 Interrupt
Reserved
CNT0 Interrupt
CNT1 Interrupt
DMA Channel 0 (PPI Rx/Tx)
DMA Channel 1 (RSI Rx/Tx)
DMA Channel 2 (SPORT0 Rx)
DMA Channel 3 (SPORT0 Tx)
DMA Channel 4 (SPORT1 Rx)
DMA Channel 5 (SPORT1 Tx)
DMA Channel 6 (SPI0 Rx/Tx)
DMA Channel 7 (SPI1 Rx/Tx)
DMA Channel 8 (UART0 Rx)
DMA Channel 9 (UART0 Tx)
DMA Channel 10 (UART1 Rx)
DMA Channel 11 (UART1 Tx)
CAN Receive
CAN Transmit
TWI
Port F Interrupt A
Port F Interrupt B
Reserved
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer 6
Timer 7
Port G Interrupt A
Port G Interrupt B
MDMA Stream 0
Interrupt (at Reset)
General-Purpose
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
IVG11
IVG11
IVG11
IVG11
IVG11
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG13
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG8
IVG8
IVG9
IVG9
IVG9
IVG9
IVG9
IVG9
Rev. 0 | Page 7 of 80 | December 2010
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ADSP-BF504/ADSP-BF504F/ADSP-BF506F
Interrupt ID
Peripheral
10
11
16
17
18
19
20
21
26
28
29
30
31
32
33
34
35
36
37
38
39
40
41
12
13
14
15
22
23
24
25
27
42
0
1
2
3
4
5
6
7
8
9
Default Core
Interrupt ID
—
—
0
0
0
0
0
2
2
2
2
3
3
0
0
0
0
0
0
1
1
2
2
3
3
3
3
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
6
IAR0
IAR0
IAR0
IAR0
IAR0
IAR1
IAR1
IAR1
IAR1
IAR2
IAR2
IAR2
IAR2
IAR2
IAR2
IAR3
IAR0
IAR0
IAR0
IAR1
IAR1
IAR1
IAR1
IAR2
IAR2
IAR3
IAR3
IAR3
IAR3
IAR3
IAR3
IAR3
IAR4
IAR4
IAR4
IAR4
IAR4
IAR4
IAR4
IAR4
IAR5
IAR5
IAR5
SIC Registers
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK0, ISR0, IWR0
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1
IMASK1, ISR1, IWR1