ADUM4160BRWZ-RL Analog Devices Inc, ADUM4160BRWZ-RL Datasheet - Page 8

• Manufacturer Part Number: ADUM4160BRWZ-RL
• Description: Full/Low Speed USB Digital Isolator
• Manufacturer: Analog Devices Inc
• Series: iCoupler®r

Specifications of ADUM4160BRWZ-RL

• Design Resources: USB Hub Isolator Circuit (CN0158) USB Cable Isolator Circuit (CN0159) USB Peripheral Isolator Circuit (CN0160)
• Inputs - Side 1/side 2: 2/2
• Number Of Channels: 4
• Isolation Rating: 5000Vrms
• Voltage - Supply: 3.1 V ~ 5.5 V
• Data Rate: 12Mbps
• Propagation Delay: 60ns
• Output Type: Logic
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Operating Temperature: -40°C ~ 105°C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 105C
• Package Type: SOIC W
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuM4160
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 9. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mnemonic Direction Description
V
GND
V
PDEN
SPU
UD−
UD+
GND
GND
DD+
DD−
PIN
SPD
V
GND
V
BUS1
DD1
DD2
BUS2
1
1
2
2
Power
Return
Power
Input
Input
I/O
I/O
Return
Return
I/O
I/O
Input
Input
Power
Return
Power
Input Power Supply for Side 1. Where the isolator is powered by the USB bus voltage, 4.5 V to 5.5 V,
connect V
V
Ground 1. Ground reference for Isolator Side 1.
Power Supply for Side 1. Where the isolator is powered by the USB bus voltage, 4.5 V to 5.5 V, the V
should be used for a bypass capacitor to GND
SPU, should be tied to this pin. Where the isolator is powered from a 3.3 V power supply, connect V
V
Pull-Down Enable. This pin is read when exiting reset. For standard operation, connect this pin to V
When connected to GND
disconnected, allowing buffer impedance measurements.
Speed Select Upstream Buffer. Active high logic input. Selects full speed slew rate, timing, and logic
conventions when SPU is high, and low speed slew rate, timing, and logic conventions when SPU is tied
low. This input must be set high via connection to V
match Pin 13.
Upstream D−.
Upstream D+.
Ground 1. Ground reference for Isolator Side 1.
Ground 2. Ground reference for Isolator Side 2.
Downstream D+.
Downstream D−.
Upstream Pull-Up Enable. PIN controls the power connection to the pull-up for the upstream port. It can
be tied to V
delayed enumeration.
Speed Select Downstream Buffer. Active high logic input. Selects full speed slew rate, timing, and logic
conventions when SPD is high, and low speed slew rate, timing, and logic conventions when SPD is tied
low. This input must be set high via connection to V
Pin 5.
Power Supply for Side 2. Where the isolator is powered by the USB bus voltage, 4.5 V to 5.5 V, the V
pin should be used for a bypass capacitor to GND
can be tied to this pin. Where the isolator is powered from a 3.3 V power supply, connect V
and to the external 3.3 V power supply. Bypass to GND
Ground 2. Ground reference for Isolator Side 2.
Input Power Supply for Side 2. Where the isolator is powered by the USB bus voltage, 4.5 V to 5.5 V,
connect V
V
BUS1
DD1
BUS2
and to the external 3.3 V power supply. Bypass to GND
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING
to V
to V
BOTH TO GND
CONNECTED, AND CONNECTING BOTH TO GND
DD1
DD2
BUS1
BUS2
DD2
and to the external 3.3 V power supply. Bypass to GND
and to the external 3.3 V power supply. Bypass to GND
to the USB power bus. Where the isolator is powered from a 3.3 V power supply, connect
to the USB power bus. Where the isolator is powered from a 3.3 V power supply, connect
for operation on power-up, or tied to an external control signal for applications requiring
1
IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
GND
GND
V
PDEN
V
BUS1
SPU
UD–
UD+
DD1
1
1
*
*
Figure 3. Pin Configuration
1
1
2
3
4
5
6
7
8
NC = NO CONNECT
while exiting from reset, the downstream pull-down resistors are
Rev. B | Page 8 of 16
ADuM4160
(Not to Scale)
TOP VIEW
16
15
14
13
12
11
10
9
V
GND
V
SPD
PIN
DD–
DD+
GND
2
BUS2
DD2
IS RECOMMENDED.
1
2
2
. Signal lines that may require pull up, such as PDEN and
*
*
2
. Signal lines that may require pull-up, such as SPD,
DD1
DD2
2
or set low via connection to GND
or low via connection to GND
is required.
1
is required.
1
2
is required.
is required.
2
, and must match
1
and must
BUS2
to V
DD2
DDI
DD2
BUS1
DD1
pin
.
to